Lines Matching +full:0 +full:x260000
61 static int have_ipu = 0;
75 #define DI_PORT 0
87 #define CPMEM_BASE 0x300000
88 #define DC_TEMPL_BASE 0x380000
92 #define TEMPLATE_SYNC(v) ((v) << 0)
100 #define OPCODE_WROD 0x18
103 #define IPU_CONF 0x200000
109 #define IPU_DISP_GEN 0x2000C4
114 #define IPU_MEM_RST 0x2000DC
116 #define IPU_MEM_RST_ALL 0x807FFFFF
117 #define IPU_CH_DB_MODE_SEL_0 0x200150
118 #define IPU_CH_DB_MODE_SEL_1 0x200154
119 #define IPU_CUR_BUF_0 0x20023C
120 #define IPU_CUR_BUF_1 0x200240
122 #define IPU_IDMAC_CH_EN_1 0x208004
123 #define IPU_IDMAC_CH_EN_2 0x208008
124 #define IPU_IDMAC_CH_PRI_1 0x208014
125 #define IPU_IDMAC_CH_PRI_2 0x208018
127 #define IPU_DI0_GENERAL 0x240000
132 #define IPU_DI0_BS_CLKGEN0 0x240004
134 #define IPU_DI0_BS_CLKGEN1 0x240008
136 #define IPU_DI0_SW_GEN0_1 0x24000C
140 #define IPU_DI0_SW_GEN1_1 0x240030
147 #define IPU_DI0_SYNC_AS_GEN 0x240054
149 #define SYNC_AS_GEN_SYNC_START(v) ((v) << 0)
150 #define IPU_DI0_DW_GEN_0 0x240058
155 #define IPU_DI0_DW_SET3_0 0x240118
157 #define DW_SET_DATA_CNT_UP(v) ((v) << 0)
158 #define IPU_DI0_STP_REP 0x240148
159 #define IPU_DI0_POL 0x240164
161 #define IPU_DI0_SCR_CONF 0x240170
163 #define IPU_DI1_GENERAL 0x248000
164 #define IPU_DI1_BS_CLKGEN0 0x248004
165 #define IPU_DI1_BS_CLKGEN1 0x248008
166 #define IPU_DI1_SW_GEN0_1 0x24800C
167 #define IPU_DI1_SW_GEN1_1 0x248030
168 #define IPU_DI1_SYNC_AS_GEN 0x248054
169 #define IPU_DI1_DW_GEN_0 0x248058
170 #define IPU_DI1_POL 0x248164
171 #define IPU_DI1_DW_SET3_0 0x248118
172 #define IPU_DI1_STP_REP 0x248148
173 #define IPU_DI1_SCR_CONF 0x248170
174 #define DMFC_RD_CHAN 0x260000
175 #define DMFC_WR_CHAN 0x260004
176 #define DMFC_WR_CHAN_BURST_SIZE_32 (0 << 6)
182 #define DMFC_WR_CHAN_DEF 0x260008
189 #define DMFC_DP_CHAN 0x26000C
198 #define DMFC_DP_CHAN_ST_ADDR_SIZE_5B(v) ((v) << 0)
199 #define DMFC_DP_CHAN_DEF 0x260010
208 #define DMFC_GENERAL_1 0x260014
210 #define DMFC_IC_CTRL 0x26001C
211 #define DMFC_IC_CTRL_DISABLED 0x2
213 #define DC_WRITE_CH_CONF_1 0x0025801C
216 #define DC_WRITE_CH_ADDR_1 0x00258020
217 #define DC_WRITE_CH_CONF_5 0x0025805C
221 #define DC_WRITE_CH_ADDR_5 0x00258060
222 #define DC_RL0_CH_5 0x00258064
223 #define DC_GEN 0x002580D4
225 #define DC_GEN_ASYNC (0 << 1)
227 #define DC_DISP_CONF2(di) (0x002580E8 + (di) * 4)
228 #define DC_MAP_CONF_0 0x00258108
229 #define DC_MAP_CONF_15 0x00258144
231 #define MAP_CONF_VAL_MASK 0xffff
233 #define MAP_CONF_PTR_MASK 0x1f
241 #define DI_SYNC_NONE 0
254 #define CH_PARAM_RESET(param) memset(param, 0, sizeof(*param))
263 0, 125, 13, (v))
265 0, 138, 12, (v))
269 1, 0, 29, (v))
273 0, 107, 3, (v))
279 0, 46, 22, (v))
281 0, 68, 22, (v))
304 0, 125, 13)
306 0, 138, 12)
310 1, 0, 29)
314 0, 107, 3)
320 0, 46, 22)
322 0, 68, 22)
344 #define IPU_PIX_FORMAT_BPP_32 0
355 DC_EVENT_NF = 0,
397 *addr = segs[0].ds_addr; in ipu_dmamap_cb()
458 …int offset0[] = {0, 10, 19, 32, 44, 45, 46, 68, 90, 94, 95, 113, 114, 117, 119, 120, 121, 122, 123… in ipu_print_channel()
459 …int offset1[] = {0, 29, 58, 78, 85, 89, 90, 93, 95, 102, 116, 119, 122, 125, 128, 133, 138, 143, 1… in ipu_print_channel()
461 param->word[0].data[0], param->word[0].data[1], in ipu_print_channel()
462 param->word[0].data[2], param->word[0].data[3], in ipu_print_channel()
463 param->word[0].data[4]); in ipu_print_channel()
465 param->word[1].data[0], param->word[1].data[1], in ipu_print_channel()
469 for (int i = 0; offset0[i + 1] != -1; i++) { in ipu_print_channel()
473 ipu_ch_param_get_value(param, 0, offset0[i], len) in ipu_print_channel()
477 for (int i = 0; offset1[i + 1] != -1; i++) { in ipu_print_channel()
488 printf("EBA0: 0x%08x\n", CH_PARAM_GET_EBA0(param)); in ipu_print_channel()
489 printf("EBA1: 0x%08x\n", CH_PARAM_GET_EBA1(param)); in ipu_print_channel()
549 if (repeat_count == 0) in ipu_config_wave_gen_1()
557 reg &= ~(0xffff); in ipu_config_wave_gen_1()
561 reg &= ~(0xffff << 16); in ipu_config_wave_gen_1()
575 IPU_WRITE4(sc, addr, 0); in ipu_reset_wave_gen()
579 IPU_WRITE4(sc, addr, 0); in ipu_reset_wave_gen()
585 reg &= ~(0xffff); in ipu_reset_wave_gen()
587 reg &= ~(0xffff << 16); in ipu_reset_wave_gen()
601 for (i = 0; i < 3; i++) { in ipu_init_microcode_template()
602 if (i == 0) in ipu_init_microcode_template()
607 glue = 0; in ipu_init_microcode_template()
611 TEMPLATE_WAVEFORM(1) | /* wave unit 0 */ in ipu_init_microcode_template()
661 map = 0; in ipu_config_timing()
664 IPU_WRITE4(sc, bs_clkgen_offset, DI_BS_CLKGEN0(div, 0)); in ipu_config_timing()
676 dw_set = DW_SET_DATA_CNT_DOWN(div * 2) | DW_SET_DATA_CNT_UP(0); in ipu_config_timing()
681 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_NONE); in ipu_config_timing()
683 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); in ipu_config_timing()
687 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_CLK); in ipu_config_timing()
689 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, DI_SYNC_CLK, in ipu_config_timing()
690 0, MODE_HSW(sc->sc_mode) * 2); in ipu_config_timing()
695 0, DI_SYNC_NONE); in ipu_config_timing()
697 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, in ipu_config_timing()
699 0, MODE_VSW(sc->sc_mode) * 2); in ipu_config_timing()
706 /* Active Data 0 */ in ipu_config_timing()
708 0, DI_SYNC_COUNTER(DI_COUNTER_HSYNC), in ipu_config_timing()
712 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); in ipu_config_timing()
715 0, DI_SYNC_CLK, MODE_HSW(sc->sc_mode) + MODE_HFP(sc->sc_mode), DI_SYNC_CLK); in ipu_config_timing()
718 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); in ipu_config_timing()
784 shift = 0; in ipu_dc_link_event()
789 reg &= ~(0xFFFF << shift); in ipu_dc_link_event()
806 shift = 0; in ipu_dc_setup_map()
807 reg &= ~(0xffff << shift); in ipu_dc_setup_map()
830 shift = 0; in ipu_dc_reset_map()
849 ipu_dc_link_event(sc, DC_EVENT_NF, 0, 0); in ipu_dc_init()
850 ipu_dc_link_event(sc, DC_EVENT_NFIELD, 0, 0); in ipu_dc_init()
851 ipu_dc_link_event(sc, DC_EVENT_EOF, 0, 0); in ipu_dc_init()
852 ipu_dc_link_event(sc, DC_EVENT_EOFIELD, 0, 0); in ipu_dc_init()
853 ipu_dc_link_event(sc, DC_EVENT_NEW_CHAN, 0, 0); in ipu_dc_init()
854 ipu_dc_link_event(sc, DC_EVENT_NEW_ADDR, 0, 0); in ipu_dc_init()
856 conf = WRITE_CH_CONF_PROG_W_SIZE(0x02) | in ipu_dc_init()
861 IPU_WRITE4(sc, DC_WRITE_CH_ADDR_5, 0x00000000); in ipu_dc_init()
889 CH_PARAM_SET_RED_OFFSET(¶m, 0); in ipu_init_buffer()
898 CH_PARAM_SET_UBO(¶m, 0); in ipu_init_buffer()
899 CH_PARAM_SET_VBO(¶m, 0); in ipu_init_buffer()
951 reg |= (1UL << (DMA_CHANNEL & 0x1f)); in ipu_init_buffer()
954 IPU_WRITE4(sc, cur_buf, (1UL << (DMA_CHANNEL & 0x1f))); in ipu_init_buffer()
968 while (i-- > 0) { in ipu_init()
974 if (i <= 0) { in ipu_init()
980 ipu_dc_reset_map(sc, 0); in ipu_init()
981 ipu_dc_setup_map(sc, 0, 0, 7, 0xff); in ipu_init()
982 ipu_dc_setup_map(sc, 0, 1, 15, 0xff); in ipu_init()
983 ipu_dc_setup_map(sc, 0, 2, 23, 0xff); in ipu_init()
992 4, 0, /* alignment, boundary */ in ipu_init()
997 dma_size, 0, /* maxsegsize, flags */ in ipu_init()
1034 reg |= (1 << (DMA_CHANNEL & 0x1f)); in ipu_init()
1054 if (device_probe_and_attach(fbd) != 0) { in ipu_init()
1059 return (0); in ipu_init()
1069 return (0); in ipu_mode_is_valid()
1097 for (n = 0; n < ei->edid_nmodes; n++) in ipu_pick_mode()
1119 edid_len = 0; in ipu_hdmi_event()
1120 if (CRTC_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { in ipu_hdmi_event()
1126 if ( edid && (edid_parse(edid, &ei) == 0)) { in ipu_hdmi_event()
1182 sc->sc_mem_rid = 0; in ipu_attach()
1190 sc->sc_irq_rid = 0; in ipu_attach()
1201 if (imx_ccm_pll_video_enable() != 0) { in ipu_attach()
1212 if (src_reset_ipu() != 0) { in ipu_attach()
1224 ipu_hdmi_event, sc, 0); in ipu_attach()
1228 return (0); in ipu_attach()
1265 DRIVER_MODULE(ipu, simplebus, ipu_driver, 0, 0);