Lines Matching +full:3 +full:x3

34 #define	  CBCDR_MMDC_CH1_AXI_PODF_SHIFT		  3
35 #define	  CBCDR_MMDC_CH1_AXI_PODF_MASK		  (7 << 3)
40 #define	  SSI_CLK_SEL_M				  0x3
57 #define	  LDB_DI0_CLK_SEL_MASK			  (3 << LDB_DI0_CLK_SEL_SHIFT)
61 #define	  CHSCCDR_IPU1_DI0_PODF_MASK		  (0x7 << 3)
62 #define	  CHSCCDR_IPU1_DI0_PODF_SHIFT		  3
66 #define	  CHSCCDR_CLK_SEL_LDB_DI0		  3
80 #define	  CCGR0_AIPS_TZ1			  (0x3 << 0)
81 #define	  CCGR0_AIPS_TZ2			  (0x3 << 2)
82 #define	  CCGR0_ABPHDMA				  (0x3 << 4)
84 #define	  CCGR1_ECSPI1				  (0x3 <<  0)
85 #define	  CCGR1_ECSPI2				  (0x3 <<  2)
86 #define	  CCGR1_ECSPI3				  (0x3 <<  4)
87 #define	  CCGR1_ECSPI4				  (0x3 <<  6)
88 #define	  CCGR1_ECSPI5				  (0x3 <<  8)
89 #define	  CCGR1_ENET				  (0x3 << 10)
90 #define	  CCGR1_EPIT1				  (0x3 << 12)
91 #define	  CCGR1_EPIT2				  (0x3 << 14)
92 #define	  CCGR1_ESAI				  (0x3 << 16)
93 #define	  CCGR1_GPT				  (0x3 << 20)
94 #define	  CCGR1_GPT_SERIAL			  (0x3 << 22)
96 #define	  CCGR2_HDMI_TX				  (0x3 << 0)
97 #define	  CCGR2_HDMI_TX_ISFR			  (0x3 << 4)
98 #define	  CCGR2_I2C1				  (0x3 << 6)
99 #define	  CCGR2_I2C2				  (0x3 << 8)
100 #define	  CCGR2_I2C3				  (0x3 << 10)
101 #define	  CCGR2_IIM				  (0x3 << 12)
102 #define	  CCGR2_IOMUX_IPT			  (0x3 << 14)
103 #define	  CCGR2_IPMUX1				  (0x3 << 16)
104 #define	  CCGR2_IPMUX2				  (0x3 << 18)
105 #define	  CCGR2_IPMUX3				  (0x3 << 20)
106 #define	  CCGR2_IPSYNC_IP2APB_TZASC1		  (0x3 << 22)
107 #define	  CCGR2_IPSYNC_IP2APB_TZASC2		  (0x3 << 24)
108 #define	  CCGR2_IPSYNC_VDOA			  (0x3 << 26)
110 #define	  CCGR3_IPU1_IPU			  (0x3 << 0)
111 #define	  CCGR3_IPU1_DI0			  (0x3 << 2)
112 #define	  CCGR3_IPU1_DI1			  (0x3 << 4)
113 #define	  CCGR3_IPU2_IPU			  (0x3 << 6)
114 #define	  CCGR3_IPU2_DI0			  (0x3 << 8)
115 #define	  CCGR3_IPU2_DI1			  (0x3 << 10)
116 #define	  CCGR3_LDB_DI0				  (0x3 << 12)
117 #define	  CCGR3_LDB_DI1				  (0x3 << 14)
118 #define	  CCGR3_MMDC_CORE_ACLK_FAST		  (0x3 << 20)
119 #define	  CCGR3_CG11				  (0x3 << 22)
120 #define	  CCGR3_MMDC_CORE_IPG			  (0x3 << 24)
121 #define	  CCGR3_CG13				  (0x3 << 26)
122 #define	  CCGR3_OCRAM				  (0x3 << 28)
124 #define	  CCGR4_PL301_MX6QFAST1_S133		  (0x3 << 8)
125 #define	  CCGR4_PL301_MX6QPER1_BCH		  (0x3 << 12)
126 #define	  CCGR4_PL301_MX6QPER2_MAIN		  (0x3 << 14)
128 #define	  CCGR5_SATA        			  (0x3 << 4)
129 #define	  CCGR5_SDMA				  (0x3 << 6)
130 #define	  CCGR5_SSI1				  (0x3 << 18)
131 #define	  CCGR5_SSI2				  (0x3 << 20)
132 #define	  CCGR5_SSI3				  (0x3 << 22)
133 #define	  CCGR5_UART				  (0x3 << 24)
134 #define	  CCGR5_UART_SERIAL			  (0x3 << 26)
136 #define	  CCGR6_USBOH3				  (0x3 << 0)
137 #define	  CCGR6_USDHC1				  (0x3 << 2)
138 #define	  CCGR6_USDHC2				  (0x3 << 4)
139 #define	  CCGR6_USDHC3				  (0x3 << 6)
140 #define	  CCGR6_USDHC4				  (0x3 << 8)
148 #define	  CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK	(3u << 19)