Lines Matching +full:0 +full:x028
32 #define CCM_CACCR 0x010
33 #define CCM_CBCDR 0x014
36 #define CCM_CSCMR1 0x01C
40 #define SSI_CLK_SEL_M 0x3
41 #define SSI_CLK_SEL_508_PFD 0
44 #define CCM_CSCMR2 0x020
46 #define CCM_CS1CDR 0x028
47 #define SSI1_CLK_PODF_SHIFT 0
51 #define SSI_CLK_PODF_MASK 0x3f
52 #define SSI_CLK_PRED_MASK 0x7
53 #define CCM_CS2CDR 0x02C
54 #define SSI2_CLK_PODF_SHIFT 0
58 #define CCM_CHSCCDR 0x034
59 #define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
61 #define CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
63 #define CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
64 #define CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT 0
65 #define CHSCCDR_CLK_SEL_PREMUXED 0
68 #define CHSCCDR_PODF_DIVIDE_BY_1 0
71 #define CCM_CSCDR2 0x038
72 #define CCM_CLPCR 0x054
73 #define CCM_CLPCR_LPM_MASK 0x03
74 #define CCM_CLPCR_LPM_RUN 0x00
75 #define CCM_CLPCR_LPM_WAIT 0x01
76 #define CCM_CLPCR_LPM_STOP 0x02
77 #define CCM_CGPR 0x064
79 #define CCM_CCGR0 0x068
80 #define CCGR0_AIPS_TZ1 (0x3 << 0)
81 #define CCGR0_AIPS_TZ2 (0x3 << 2)
82 #define CCGR0_ABPHDMA (0x3 << 4)
83 #define CCM_CCGR1 0x06C
84 #define CCGR1_ECSPI1 (0x3 << 0)
85 #define CCGR1_ECSPI2 (0x3 << 2)
86 #define CCGR1_ECSPI3 (0x3 << 4)
87 #define CCGR1_ECSPI4 (0x3 << 6)
88 #define CCGR1_ECSPI5 (0x3 << 8)
89 #define CCGR1_ENET (0x3 << 10)
90 #define CCGR1_EPIT1 (0x3 << 12)
91 #define CCGR1_EPIT2 (0x3 << 14)
92 #define CCGR1_ESAI (0x3 << 16)
93 #define CCGR1_GPT (0x3 << 20)
94 #define CCGR1_GPT_SERIAL (0x3 << 22)
95 #define CCM_CCGR2 0x070
96 #define CCGR2_HDMI_TX (0x3 << 0)
97 #define CCGR2_HDMI_TX_ISFR (0x3 << 4)
98 #define CCGR2_I2C1 (0x3 << 6)
99 #define CCGR2_I2C2 (0x3 << 8)
100 #define CCGR2_I2C3 (0x3 << 10)
101 #define CCGR2_IIM (0x3 << 12)
102 #define CCGR2_IOMUX_IPT (0x3 << 14)
103 #define CCGR2_IPMUX1 (0x3 << 16)
104 #define CCGR2_IPMUX2 (0x3 << 18)
105 #define CCGR2_IPMUX3 (0x3 << 20)
106 #define CCGR2_IPSYNC_IP2APB_TZASC1 (0x3 << 22)
107 #define CCGR2_IPSYNC_IP2APB_TZASC2 (0x3 << 24)
108 #define CCGR2_IPSYNC_VDOA (0x3 << 26)
109 #define CCM_CCGR3 0x074
110 #define CCGR3_IPU1_IPU (0x3 << 0)
111 #define CCGR3_IPU1_DI0 (0x3 << 2)
112 #define CCGR3_IPU1_DI1 (0x3 << 4)
113 #define CCGR3_IPU2_IPU (0x3 << 6)
114 #define CCGR3_IPU2_DI0 (0x3 << 8)
115 #define CCGR3_IPU2_DI1 (0x3 << 10)
116 #define CCGR3_LDB_DI0 (0x3 << 12)
117 #define CCGR3_LDB_DI1 (0x3 << 14)
118 #define CCGR3_MMDC_CORE_ACLK_FAST (0x3 << 20)
119 #define CCGR3_CG11 (0x3 << 22)
120 #define CCGR3_MMDC_CORE_IPG (0x3 << 24)
121 #define CCGR3_CG13 (0x3 << 26)
122 #define CCGR3_OCRAM (0x3 << 28)
123 #define CCM_CCGR4 0x078
124 #define CCGR4_PL301_MX6QFAST1_S133 (0x3 << 8)
125 #define CCGR4_PL301_MX6QPER1_BCH (0x3 << 12)
126 #define CCGR4_PL301_MX6QPER2_MAIN (0x3 << 14)
127 #define CCM_CCGR5 0x07C
128 #define CCGR5_SATA (0x3 << 4)
129 #define CCGR5_SDMA (0x3 << 6)
130 #define CCGR5_SSI1 (0x3 << 18)
131 #define CCGR5_SSI2 (0x3 << 20)
132 #define CCGR5_SSI3 (0x3 << 22)
133 #define CCGR5_UART (0x3 << 24)
134 #define CCGR5_UART_SERIAL (0x3 << 26)
135 #define CCM_CCGR6 0x080
136 #define CCGR6_USBOH3 (0x3 << 0)
137 #define CCGR6_USDHC1 (0x3 << 2)
138 #define CCGR6_USDHC2 (0x3 << 4)
139 #define CCGR6_USDHC3 (0x3 << 6)
140 #define CCGR6_USDHC4 (0x3 << 8)
141 #define CCM_CMEOR 0x088
143 #define CCM_ANALOG_PLL_VIDEO 0x000040a0
150 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7f << 0)
151 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0
153 #define CCM_ANALOG_PLL_VIDEO_NUM 0x000040b0
154 #define CCM_ANALOG_PLL_VIDEO_DENOM 0x000040c0
156 #define CCM_ANALOG_PLL_ENET 0x000040e0