Lines Matching +full:0 +full:x4060
55 #define PCI_ID_VAL3 0x43c
56 #define CLASS_SHIFT 0x10
57 #define SUBCLASS_SHIFT 0x8
59 #define REG_CONTROLLER_HW_REV 0x406c
60 #define REG_BRIDGE_CTRL 0x9210
61 #define BRIDGE_DISABLE_FLAG 0x1
62 #define BRIDGE_RESET_FLAG 0x2
63 #define REG_PCIE_HARD_DEBUG 0x4204
64 #define REG_DMA_CONFIG 0x4008
65 #define REG_DMA_WINDOW_LOW 0x4034
66 #define REG_DMA_WINDOW_HIGH 0x4038
67 #define REG_DMA_WINDOW_1 0x403c
68 #define REG_BRIDGE_GISB_WINDOW 0x402c
69 #define REG_BRIDGE_STATE 0x4068
70 #define REG_BRIDGE_LINK_STATE 0x00bc
71 #define REG_BUS_WINDOW_LOW 0x400c
72 #define REG_BUS_WINDOW_HIGH 0x4010
73 #define REG_CPU_WINDOW_LOW 0x4070
74 #define REG_CPU_WINDOW_START_HIGH 0x4080
75 #define REG_CPU_WINDOW_END_HIGH 0x4084
77 #define REG_MSI_ADDR_LOW 0x4044
78 #define REG_MSI_ADDR_HIGH 0x4048
79 #define REG_MSI_CONFIG 0x404c
80 #define REG_MSI_CLR 0x4508
81 #define REG_MSI_MASK_CLR 0x4514
82 #define REG_MSI_RAISED 0x4500
83 #define REG_MSI_EOI 0x4060
86 #define REG_EP_CONFIG_CHOICE 0x9000
87 #define REG_EP_CONFIG_DATA 0x8000
89 #define L1SS_ENABLE 0x00200000
90 #define CLKREQ_ENABLE 0x2
106 #define DMA_HIGH_LIMIT 0x3c000000
107 #define MAX_MEMORY_LOG2 0x21
108 #define REG_VALUE_DMA_WINDOW_LOW (MAX_MEMORY_LOG2 - 0xf)
109 #define REG_VALUE_DMA_WINDOW_HIGH 0x0
110 #define DMA_WINDOW_ENABLE 0x3000
112 (((MAX_MEMORY_LOG2 - 0xf) << 0x1b) | DMA_WINDOW_ENABLE)
114 #define REG_VALUE_MSI_CONFIG 0xffe06540
138 {NULL, 0}
196 bcm_pcib_set_reg(sc, REG_PCIE_HARD_DEBUG, 0); in bcm_pcib_reset_controller()
218 int error = 0, i; in bcm_pcib_check_ranges()
221 ranges = &sc->base.base.ranges[0]; in bcm_pcib_check_ranges()
224 if (ranges[0].size == 0) { in bcm_pcib_check_ranges()
226 "(pci addr: 0x%jx, cpu addr: 0x%jx) has zero size.\n", in bcm_pcib_check_ranges()
227 ranges[0].pci_base, ranges[0].phys_base); in bcm_pcib_check_ranges()
236 if (ranges[i].size > 0) in bcm_pcib_check_ranges()
238 "note: outbound memory range %d (pci addr: 0x%jx, " in bcm_pcib_check_ranges()
239 "cpu addr: 0x%jx, size: 0x%jx) will be ignored.\n", in bcm_pcib_check_ranges()
252 case 0: in bcm_pcib_link_state_string()
276 if (bus == 0 && slot == 0 && func == 0) in bcm_get_offset_and_prepare_config()
284 func_index = PCIE_ADDR_OFFSET(bus, slot, func, 0); in bcm_get_offset_and_prepare_config()
300 if (bus == 0 && slot == 0 && func == 0) in bcm_pcib_is_valid_quad()
302 if (bus == 0) in bcm_pcib_is_valid_quad()
304 * Probing other slots and funcs on bus 0 will lock up the in bcm_pcib_is_valid_quad()
322 return (~0U); in bcm_pcib_read_config()
338 data = ~0U; in bcm_pcib_read_config()
432 for (first_int = 0; first_int + count < NUM_MSI; ) { in bcm_pcib_alloc_msi()
450 for (i = 0; i < count; ++i) { in bcm_pcib_alloc_msi()
458 return (0); in bcm_pcib_alloc_msi()
472 *data = (REG_VALUE_MSI_CONFIG & 0xffff) | msi_msg->irq; in bcm_pcib_map_msi()
473 return (0); in bcm_pcib_map_msi()
487 for (i = 0; i < count; i++) { in bcm_pcib_release_msi()
493 return (0); in bcm_pcib_release_msi()
505 sc->msi_addr = 0xffffffffc; in bcm_pcib_msi_attach()
508 bcm_pcib_set_reg(sc, REG_MSI_CLR, 0xffffffff); in bcm_pcib_msi_attach()
523 if (error != 0) { in bcm_pcib_msi_attach()
529 for (i = 0; i < NUM_MSI; i++) { in bcm_pcib_msi_attach()
531 error = intr_isrc_register(&sc->msi_isrcs[i].isrc, dev, 0, in bcm_pcib_msi_attach()
533 if (error != 0) { in bcm_pcib_msi_attach()
545 if (error != 0) in bcm_pcib_msi_attach()
550 bcm_pcib_set_reg(sc, REG_MSI_MASK_CLR, 0xffffffff); in bcm_pcib_msi_attach()
551 bcm_pcib_set_reg(sc, REG_MSI_ADDR_LOW, (sc->msi_addr & 0xffffffff) | 1); in bcm_pcib_msi_attach()
555 return (0); in bcm_pcib_msi_attach()
576 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMBASE_1, 2); in bcm_pcib_relocate_bridge_window()
577 base = PCI_PPBMEMBASE(0, val); in bcm_pcib_relocate_bridge_window()
579 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, 2); in bcm_pcib_relocate_bridge_window()
580 size = PCI_PPBMEMLIMIT(0, val) - base; in bcm_pcib_relocate_bridge_window()
582 new_base = sc->base.base.ranges[0].pci_base; in bcm_pcib_relocate_bridge_window()
584 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMBASE_1, val, 2); in bcm_pcib_relocate_bridge_window()
588 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, val, 2); in bcm_pcib_relocate_bridge_window()
595 return (((phys_base >> 0x10) & 0xfff0) | in encode_cpu_window_low()
596 ((phys_base + size - 1) & 0xfff00000)); in encode_cpu_window_low()
603 return ((phys_base >> 0x20) & 0xff); in encode_cpu_window_start_high()
610 return (((phys_base + size - 1) >> 0x20) & 0xff); in encode_cpu_window_end_high()
630 1, 0, /* alignment, bounds */ in bcm_pcib_attach()
637 0, /* flags */ in bcm_pcib_attach()
640 if (error != 0) in bcm_pcib_attach()
644 if (error != 0) in bcm_pcib_attach()
648 if (error != 0) in bcm_pcib_attach()
655 hardware_rev = bcm_pcib_read_reg(sc, REG_CONTROLLER_HW_REV) & 0xffff; in bcm_pcib_attach()
656 device_printf(dev, "hardware identifies as revision 0x%x.\n", in bcm_pcib_attach()
667 bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0); in bcm_pcib_attach()
668 bcm_pcib_set_reg(sc, REG_DMA_WINDOW_1, 0); in bcm_pcib_attach()
673 for(tries = 0; ; ++tries) { in bcm_pcib_attach()
676 if ((bridge_state & 0x30) == 0x30) in bcm_pcib_attach()
689 link_state = bcm_pcib_read_reg(sc, REG_BRIDGE_LINK_STATE) >> 0x10; in bcm_pcib_attach()
704 pci_base = sc->base.base.ranges[0].pci_base; in bcm_pcib_attach()
705 phys_base = sc->base.base.ranges[0].phys_base; in bcm_pcib_attach()
706 size = sc->base.base.ranges[0].size; in bcm_pcib_attach()
708 bcm_pcib_set_reg(sc, REG_BUS_WINDOW_LOW, pci_base & 0xffffffff); in bcm_pcib_attach()
743 if (error != 0) in bcm_pcib_attach()
749 return (0); in bcm_pcib_attach()
778 DRIVER_MODULE(bcm_pcib, simplebus, bcm_pcib_driver, 0, 0);