38  * alt-0 - rubbish SDHCI  (0x7e202000) aka sdhost
39  * alt-3 - advanced SDHCI (0x7e300000) aka sdhci/mmc/sdio
44  *         brcm,pins = <0x30 0x31 0x32 0x33 0x34 0x35>;
45  *         brcm,function = <0x7>;
46  *         brcm,pull = <0x0 0x2 0x2 0x2 0x2 0x2>;
47  *         phandle = <0x17>;
50  *         brcm,pins = <0x22 0x23 0x24 0x25 0x26 0x27>;
51  *         brcm,function = <0x4>;
52  *         brcm,pull = <0x0 0x2 0x2 0x2 0x2 0x2>;
53  *         phandle = <0x18>;
59  *         brcm,pins = <0x30 0x31 0x32 0x33 0x34 0x35>;
60  *         brcm,function = <0x4>;
61  *         brcm,pull = <0x0 0x2 0x2 0x2 0x2 0x2>;
62  *         phandle = <0x17>;
65  *         brcm,pins = <0x22 0x23 0x24 0x25 0x26 0x27>;
66  *         brcm,function = <0x7>;
67  *         brcm,pull = <0x0 0x2 0x2 0x2 0x2 0x2>;
68  *         phandle = <0x18>;
109 #define HC_COMMAND		0x00	/* Command and flags */
110 #define HC_ARGUMENT		0x04
111 #define HC_TIMEOUTCOUNTER	0x08
112 #define HC_CLOCKDIVISOR		0x0c
113 #define HC_RESPONSE_0		0x10
114 #define HC_RESPONSE_1		0x14
115 #define HC_RESPONSE_2		0x18
116 #define HC_RESPONSE_3		0x1c
117 #define HC_HOSTSTATUS		0x20
118 #define HC_POWER		0x30
119 #define HC_DEBUG		0x34
120 #define HC_HOSTCONFIG		0x38
121 #define HC_BLOCKSIZE		0x3c
122 #define HC_DATAPORT		0x40
123 #define HC_BLOCKCOUNT		0x50
126 #define HC_CMD_ENABLE			0x8000
127 #define HC_CMD_FAILED			0x4000
128 #define HC_CMD_BUSY			0x0800
129 #define HC_CMD_RESPONSE_NONE		0x0400
130 #define HC_CMD_RESPONSE_LONG		0x0200
131 #define HC_CMD_WRITE			0x0080
132 #define HC_CMD_READ			0x0040
133 #define HC_CMD_COMMAND_MASK		0x003f
135 #define HC_CLOCKDIVISOR_MAXVAL		0x07ff
138 #define HC_HSTST_HAVEDATA		0x0001
139 #define HC_HSTST_ERROR_FIFO		0x0008
140 #define HC_HSTST_ERROR_CRC7		0x0010
141 #define HC_HSTST_ERROR_CRC16		0x0020
142 #define HC_HSTST_TIMEOUT_CMD		0x0040
143 #define HC_HSTST_TIMEOUT_DATA		0x0080
144 #define HC_HSTST_INT_BLOCK		0x0200
145 #define HC_HSTST_INT_BUSY		0x0400
147 #define HC_HSTST_RESET			0xffff
156 #define HC_HSTCF_INTBUS_WIDE		0x0002
157 #define HC_HSTCF_EXTBUS_4BIT		0x0004
158 #define HC_HSTCF_SLOW_CARD		0x0008
159 #define HC_HSTCF_INT_DATA		0x0010
160 #define HC_HSTCF_INT_BLOCK		0x0100
161 #define HC_HSTCF_INT_BUSY		0x0400
166 #define HC_DBG_FIFO_THRESH_MASK		0x001f
173 #define HC_TIMEOUT_DEFAULT	0x00f00000
177 static int bcm2835_sdhost_debug = 0;
183     &bcm2835_sdhost_debug, 0, "bcm2835-sdhost Debug level");
187 		if (bcm2835_sdhost_debug > 0) \
189 	} while (0)
198 	{NULL,				0}
257 	return ((val >> (off & 3)*8) & 0xffff);  in RD2()
268 	return ((val >> (off & 3)*8) & 0xff);  in RD1()
277 	val32 &= ~(0xffff << (off & 3)*8);  in WR2()
288 	val32 &= ~(0xff << (off & 3)*8);  in WR1()
298 	if (bcm2835_sdhost_debug > 0 || error > 0) {  in bcm_sdhost_print_regs()
301 		printf("HC_COMMAND:        0x%08x\n",  in bcm_sdhost_print_regs()
303 		printf("HC_ARGUMENT:       0x%08x\n",  in bcm_sdhost_print_regs()
305 		printf("HC_TIMEOUTCOUNTER: 0x%08x\n",  in bcm_sdhost_print_regs()
307 		printf("HC_CLOCKDIVISOR:   0x%08x\n",  in bcm_sdhost_print_regs()
309 		printf("HC_RESPONSE_0:     0x%08x\n",  in bcm_sdhost_print_regs()
311 		printf("HC_RESPONSE_1:     0x%08x\n",  in bcm_sdhost_print_regs()
313 		printf("HC_RESPONSE_2:     0x%08x\n",  in bcm_sdhost_print_regs()
315 		printf("HC_RESPONSE_3:     0x%08x\n",  in bcm_sdhost_print_regs()
317 		printf("HC_HOSTSTATUS:     0x%08x\n",  in bcm_sdhost_print_regs()
319 		printf("HC_POWER:          0x%08x\n",  in bcm_sdhost_print_regs()
321 		printf("HC_DEBUG:          0x%08x\n",  in bcm_sdhost_print_regs()
323 		printf("HC_HOSTCONFIG:     0x%08x\n",  in bcm_sdhost_print_regs()
325 		printf("HC_BLOCKSIZE:      0x%08x\n",  in bcm_sdhost_print_regs()
327 		printf("HC_BLOCKCOUNT:     0x%08x\n",  in bcm_sdhost_print_regs()
332 		printf("%04d | HC_COMMAND: 0x%08x HC_ARGUMENT: 0x%08x "  in bcm_sdhost_print_regs()
333 		    "HC_HOSTSTATUS: 0x%08x HC_HOSTCONFIG: 0x%08x\n",  in bcm_sdhost_print_regs()
346 	WR4(sc, HC_POWER, 0);  in bcm_sdhost_reset()
348 	WR4(sc, HC_COMMAND, 0);  in bcm_sdhost_reset()
349 	WR4(sc, HC_ARGUMENT, 0);  in bcm_sdhost_reset()
351 	WR4(sc, HC_CLOCKDIVISOR, 0);  in bcm_sdhost_reset()
353 	WR4(sc, HC_HOSTCONFIG, 0);  in bcm_sdhost_reset()
354 	WR4(sc, HC_BLOCKSIZE, 0);  in bcm_sdhost_reset()
355 	WR4(sc, HC_BLOCKCOUNT, 0);  in bcm_sdhost_reset()
386 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in bcm_sdhost_probe()
410 	sc->cmdbusy = 0;  in bcm_sdhost_attach()
411 	sc->mmc_app_cmd = 0;  in bcm_sdhost_attach()
412 	sc->sdhci_int_status = 0;  in bcm_sdhost_attach()
413 	sc->sdhci_signal_enable = 0;  in bcm_sdhost_attach()
414 	sc->sdhci_present_state = 0;  in bcm_sdhost_attach()
415 	sc->sdhci_blocksize = 0;  in bcm_sdhost_attach()
416 	sc->sdhci_blockcount = 0;  in bcm_sdhost_attach()
418 	sc->sdcard_rca = 0;  in bcm_sdhost_attach()
421 	err = 0;  in bcm_sdhost_attach()
426 	rid = 0;  in bcm_sdhost_attach()
440 	bcm_sdhost_print_regs(sc, &sc->sc_slot, __LINE__, 0);  in bcm_sdhost_attach()
442 	rid = 0;  in bcm_sdhost_attach()
458 	sc->sc_slot.caps = 0;  in bcm_sdhost_attach()
463 	sc->sc_slot.quirks = 0;  in bcm_sdhost_attach()
467 	sc->sc_slot.opt = 0;  in bcm_sdhost_attach()
473 	sdhci_init_slot(dev, &sc->sc_slot, 0);  in bcm_sdhost_attach()
480 	return (0);  in bcm_sdhost_attach()
486 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);  in bcm_sdhost_attach()
488 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);  in bcm_sdhost_attach()
503  * rv 0 --> command finished
513 	while ((RD4(sc, HC_COMMAND) & HC_CMD_ENABLE) && --timeout > 0) {  in bcm_sdhost_waitcommand()
517 	return ((timeout > 0) ? 0 : 1);  in bcm_sdhost_waitcommand()
530 	i = 0;  in bcm_sdhost_waitcommand_status()
539 		    __func__, cdst, (cdst & 0x0e00) >> 9);  in bcm_sdhost_waitcommand_status()
544 			    (cdst & 0x0e00) >> 9);  in bcm_sdhost_waitcommand_status()
548 	} while (((cdst & 0x0e00) >> 9) != 4);  in bcm_sdhost_waitcommand_status()
550 	return (0);  in bcm_sdhost_waitcommand_status()
574 			    "HC_CMD_READ or HC_CMD_WRITE: cmd=%0x8 "  in bcm_sdhost_intr()
615 			WR4(sc, HC_ARGUMENT, 0x00000000);  in bcm_sdhost_intr()
627 			if (bcm_sdhost_waitcommand_status(sc) != 0)  in bcm_sdhost_intr()
651 	return (0);  in bcm_sdhost_get_ro()
686 	flags = val & 0xff;  in bcm_sdhost_command()
731 			bcm_sdhost_print_regs(sc, &sc->sc_slot, __LINE__, 0);  in bcm_sdhost_command()
748 		slot->data_done = 0;  in bcm_sdhost_command()
756 		if (bcm_sdhost_waitcommand_status(sc) != 0) {  in bcm_sdhost_command()
774 	bcm_sdhost_print_regs(sc, &sc->sc_slot, __LINE__, 0);  in bcm_sdhost_command()
785 		slot->curcmd->error = 0;  in bcm_sdhost_command()
788 		sc->mmc_app_cmd = 0;  in bcm_sdhost_command()
795 	sc->cmdbusy = 0;  in bcm_sdhost_command()
820 		val2 = 0;  in bcm_sdhost_read_1()
828 		val2 = (val1 == 1) ? 0x0f : 0;  in bcm_sdhost_read_1()
834 		val2 = 0;  in bcm_sdhost_read_1()
838 		val2 = 0;  in bcm_sdhost_read_1()
842 		val2 = 0;  in bcm_sdhost_read_1()
846 		val2 = 0;  in bcm_sdhost_read_1()
850 		val2 = 0;  in bcm_sdhost_read_1()
854 		val2 = 0;  in bcm_sdhost_read_1()
884 		val2 = 0;  in bcm_sdhost_read_2()
896 		val2 = 0;  in bcm_sdhost_read_2()
900 		val2 = 0;  in bcm_sdhost_read_2()
904 		val2 = 0;  in bcm_sdhost_read_2()
908 		val2 = 0;  in bcm_sdhost_read_2()
912 		val2 = 0;  in bcm_sdhost_read_2()
932 		val2 = 0;  in bcm_sdhost_read_4()
937 		    (RD4(sc, HC_ARGUMENT) & 0x0000ffff);  in bcm_sdhost_read_4()
939 	case SDHCI_RESPONSE + 0:  in bcm_sdhost_read_4()
941 		dprintf("%s: SDHCI_RESPONSE+0       %08x\n", __func__, val2);  in bcm_sdhost_read_4()
957 		val2 = 0;  in bcm_sdhost_read_4()
971 		val2 = 0;  in bcm_sdhost_read_4()
979 		val2 = 0;  in bcm_sdhost_read_4()
983 		val2 = 0;  in bcm_sdhost_read_4()
987 		val2 = 0;  in bcm_sdhost_read_4()
991 		val2 = 0;  in bcm_sdhost_read_4()
995 		val2 = 0;  in bcm_sdhost_read_4()
1017 	for (i = 0; i < count;) {  in bcm_sdhost_read_multi_4()
1019 		avail = ((edm >> 4) & 0x1f);  in bcm_sdhost_read_multi_4()
1022 		if (avail > 0)  in bcm_sdhost_read_multi_4()
1053 		val2 = (val != 0) ? 1 : 0;  in bcm_sdhost_write_1()
1117 		/* get crc16 errors with cdiv=0 */  in bcm_sdhost_write_2()
1118 		if (val2 == 0)  in bcm_sdhost_write_2()
1177 		if (val != 0)  in bcm_sdhost_write_4()
1225 	for (i = 0; i < count;) {  in bcm_sdhost_write_multi_4()
1227 		space = HC_FIFO_SIZE - ((edm >> 4) & 0x1f);  in bcm_sdhost_write_multi_4()
1230 		if (space > 0)  in bcm_sdhost_write_multi_4()
1238 	while (((RD4(sc, HC_DEBUG) >> 4) & 0x1f) > 0)  in bcm_sdhost_write_multi_4()