352 	struct gpio_irqsrc 	*gpio_pic_irqsrc;  member
1222 		if (!sc->gpio_pic_irqsrc[irq].enabled)  in aw_gpio_intr()
1225 		reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank));  in aw_gpio_intr()
1226 		if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum)))  in aw_gpio_intr()
1229 		isrc = &sc->gpio_pic_irqsrc[irq].isrc;  in aw_gpio_intr()
1260 	sc->gpio_pic_irqsrc = malloc(sizeof(*sc->gpio_pic_irqsrc) * nirqs,  in aw_gpio_register_isrcs()
1266 		sc->gpio_pic_irqsrc[nirqs].pin = pin;  in aw_gpio_register_isrcs()
1267 		sc->gpio_pic_irqsrc[nirqs].bank = sc->conf->padconf->pins[pin].eint_bank;  in aw_gpio_register_isrcs()
1268 		sc->gpio_pic_irqsrc[nirqs].intnum = sc->conf->padconf->pins[pin].eint_num;  in aw_gpio_register_isrcs()
1269 		sc->gpio_pic_irqsrc[nirqs].intfunc = sc->conf->padconf->pins[pin].eint_func;  in aw_gpio_register_isrcs()
1270 		sc->gpio_pic_irqsrc[nirqs].irq = nirqs;  in aw_gpio_register_isrcs()
1271 		sc->gpio_pic_irqsrc[nirqs].mode = GPIO_INTR_CONFORM;  in aw_gpio_register_isrcs()
1273 		err = intr_isrc_register(&sc->gpio_pic_irqsrc[nirqs].isrc,  in aw_gpio_register_isrcs()
1296 	reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));  in aw_gpio_pic_disable_intr_locked()
1297 	reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum);  in aw_gpio_pic_disable_intr_locked()
1298 	AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);  in aw_gpio_pic_disable_intr_locked()
1300 	sc->gpio_pic_irqsrc[irq].enabled = false;  in aw_gpio_pic_disable_intr_locked()
1325 	reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));  in aw_gpio_pic_enable_intr()
1326 	reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum;  in aw_gpio_pic_enable_intr()
1327 	AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);  in aw_gpio_pic_enable_intr()
1330 	sc->gpio_pic_irqsrc[irq].enabled = true;  in aw_gpio_pic_enable_intr()
1343 		if (sc->gpio_pic_irqsrc[pin].pin == irq)  in aw_gpio_pic_map_gpio()
1390 		*isrcp = &sc->gpio_pic_irqsrc[irq].isrc;  in aw_gpio_pic_map_intr()
1419 	pinidx = (sc->gpio_pic_irqsrc[irq].intnum % 8) * 4;  in aw_gpio_pic_setup_intr()
1441 	sc->gpio_pic_irqsrc[irq].oldfunc = aw_gpio_get_function(sc,  in aw_gpio_pic_setup_intr()
1442 	    sc->gpio_pic_irqsrc[irq].pin);  in aw_gpio_pic_setup_intr()
1443 	aw_gpio_set_function(sc, sc->gpio_pic_irqsrc[irq].pin,  in aw_gpio_pic_setup_intr()
1444 	    sc->gpio_pic_irqsrc[irq].intfunc);  in aw_gpio_pic_setup_intr()
1448 	    AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,  in aw_gpio_pic_setup_intr()
1449 	    sc->gpio_pic_irqsrc[irq].intnum));  in aw_gpio_pic_setup_intr()
1453 	    AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,  in aw_gpio_pic_setup_intr()
1454 	    sc->gpio_pic_irqsrc[irq].intnum),  in aw_gpio_pic_setup_intr()