1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
69  * Compute ceil(log2(x)).  Returns -1 if x is zero.
75 	return (x == 0 ? -1 : order_base_2(x));  in log2()
118 	 * no multi-core or SMT.  in x86_emulate_cpuid()
158 				logical_cpus = MIN(0xFF, threads * cores - 1);  in x86_emulate_cpuid()
206 			 * features are hardware-specific and exposing  in x86_emulate_cpuid()
220 			 * - host TSC frequency is invariant  in x86_emulate_cpuid()
221 			 * - host TSCs are synchronized across physical cpus  in x86_emulate_cpuid()
241 			 * package, and L1 and L2 local to a core.  in x86_emulate_cpuid()
268 			logical_cpus = MIN(0xfff, logical_cpus - 1);  in x86_emulate_cpuid()
271 			regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0;  in x86_emulate_cpuid()
274 			 * ecx: Number of cache ways for non-fully  in x86_emulate_cpuid()
294 			threads = MIN(0xFF, threads - 1);  in x86_emulate_cpuid()
406 				regs[0] |= (cores - 1) << 26;  in x86_emulate_cpuid()
409 				 * - L1 and L2 are shared only by the logical  in x86_emulate_cpuid()
411 				 * - L3 and above are shared by all logical  in x86_emulate_cpuid()
418 				regs[0] |= (logical_cpus - 1) << 14;  in x86_emulate_cpuid()
436 				 * Expose known-safe features.  in x86_emulate_cpuid()
530 			if (!limits->xsave_enabled) {  in x86_emulate_cpuid()
545 				 * maximum save area size is  in x86_emulate_cpuid()
547 				 * save area size.  Since this runs  in x86_emulate_cpuid()
550 				 * save area size is correct as-is.  in x86_emulate_cpuid()
552 				regs[0] &= limits->xcr0_allowed;  in x86_emulate_cpuid()
553 				regs[2] = limits->xsave_max_size;  in x86_emulate_cpuid()
554 				regs[3] &= (limits->xcr0_allowed >> 32);  in x86_emulate_cpuid()
566 				 * pass through as-is, otherwise return  in x86_emulate_cpuid()
569 				if (!(limits->xcr0_allowed & (1ul << param))) {  in x86_emulate_cpuid()
601 			 * local APIC frequency..  in x86_emulate_cpuid()
636 	 * CPUID clears the upper 32-bits of the long-mode registers.  in x86_emulate_cpuid()
647 vm_cpuid_capability(struct vcpu *vcpu, enum vm_cpuid_capability cap)  in vm_cpuid_capability()  argument
651 	KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d",  in vm_cpuid_capability()
652 	    __func__, cap));  in vm_cpuid_capability()
658 	switch (cap) {  in vm_cpuid_capability()
672 		panic("%s: unknown vm_cpu_capability %d", __func__, cap);  in vm_cpuid_capability()
685 		*val = mtrr->def_type;  in vm_rdmtrr()
688 		*val = mtrr->fixed4k[num - MSR_MTRR4kBase];  in vm_rdmtrr()
691 		*val = mtrr->fixed16k[num - MSR_MTRR16kBase];  in vm_rdmtrr()
694 		*val = mtrr->fixed64k;  in vm_rdmtrr()
696 	case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {  in vm_rdmtrr()
697 		u_int offset = num - MSR_MTRRVarBase;  in vm_rdmtrr()
699 			*val = mtrr->var[offset / 2].base;  in vm_rdmtrr()
701 			*val = mtrr->var[offset / 2].mask;  in vm_rdmtrr()
706 		return (-1);  in vm_rdmtrr()
718 		return (-1);  in vm_wrmtrr()
722 			return (-1);  in vm_wrmtrr()
724 		mtrr->def_type = val;  in vm_wrmtrr()
727 		mtrr->fixed4k[num - MSR_MTRR4kBase] = val;  in vm_wrmtrr()
730 		mtrr->fixed16k[num - MSR_MTRR16kBase] = val;  in vm_wrmtrr()
733 		mtrr->fixed64k = val;  in vm_wrmtrr()
735 	case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {  in vm_wrmtrr()
736 		u_int offset = num - MSR_MTRRVarBase;  in vm_wrmtrr()
740 				return (-1);  in vm_wrmtrr()
742 			mtrr->var[offset / 2].base = val;  in vm_wrmtrr()
746 				return (-1);  in vm_wrmtrr()
748 			mtrr->var[offset / 2].mask = val;  in vm_wrmtrr()
753 		return (-1);  in vm_wrmtrr()