1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
34 #include <machine/clock.h>
35 #include <machine/cpufunc.h>
36 #include <machine/md_var.h>
37 #include <machine/segments.h>
38 #include <machine/specialreg.h>
39 #include <machine/vmm.h>
64  * Compute ceil(log2(x)).  Returns -1 if x is zero.
70 	return (x == 0 ? -1 : order_base_2(x));  in log2()
81 	int error, enable_invpcid, enable_rdpid, enable_rdtscp, level,  in x86_emulate_cpuid()  local
98 	 * available level instead.  in x86_emulate_cpuid()
113 	 * no multi-core or SMT.  in x86_emulate_cpuid()
153 				logical_cpus = MIN(0xFF, threads * cores - 1);  in x86_emulate_cpuid()
201 			 * features are hardware-specific and exposing  in x86_emulate_cpuid()
215 			 * - host TSC frequency is invariant  in x86_emulate_cpuid()
216 			 * - host TSCs are synchronized across physical cpus  in x86_emulate_cpuid()
243 				level = 1;  in x86_emulate_cpuid()
248 				level = 2;  in x86_emulate_cpuid()
253 				level = 3;  in x86_emulate_cpuid()
258 				level = 0;  in x86_emulate_cpuid()
263 			logical_cpus = MIN(0xfff, logical_cpus - 1);  in x86_emulate_cpuid()
265 			    (level << 5) | func;  in x86_emulate_cpuid()
266 			regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0;  in x86_emulate_cpuid()
269 			 * ecx: Number of cache ways for non-fully  in x86_emulate_cpuid()
289 			threads = MIN(0xFF, threads - 1);  in x86_emulate_cpuid()
379 			 * Advertise the Machine Check and MTRR capability.  in x86_emulate_cpuid()
401 				regs[0] |= (cores - 1) << 26;  in x86_emulate_cpuid()
404 				 * - L1 and L2 are shared only by the logical  in x86_emulate_cpuid()
406 				 * - L3 and above are shared by all logical  in x86_emulate_cpuid()
410 				level = (regs[0] >> 5) & 0x7;  in x86_emulate_cpuid()
411 				if (level >= 3)  in x86_emulate_cpuid()
413 				regs[0] |= (logical_cpus - 1) << 14;  in x86_emulate_cpuid()
431 				 * Expose known-safe features.  in x86_emulate_cpuid()
493 					level = CPUID_TYPE_SMT;  in x86_emulate_cpuid()
500 					level = CPUID_TYPE_CORE;  in x86_emulate_cpuid()
507 					level = 0;  in x86_emulate_cpuid()
513 				regs[2] = (level << 8) | (param & 0xff);  in x86_emulate_cpuid()
525 			if (!limits->xsave_enabled) {  in x86_emulate_cpuid()
545 				 * save area size is correct as-is.  in x86_emulate_cpuid()
547 				regs[0] &= limits->xcr0_allowed;  in x86_emulate_cpuid()
548 				regs[2] = limits->xsave_max_size;  in x86_emulate_cpuid()
549 				regs[3] &= (limits->xcr0_allowed >> 32);  in x86_emulate_cpuid()
561 				 * pass through as-is, otherwise return  in x86_emulate_cpuid()
564 				if (!(limits->xcr0_allowed & (1ul << param))) {  in x86_emulate_cpuid()
582 			 * This is already hidden at a high level by masking of  in x86_emulate_cpuid()
624 	 * CPUID clears the upper 32-bits of the long-mode registers.  in x86_emulate_cpuid()
673 		*val = mtrr->def_type;  in vm_rdmtrr()
676 		*val = mtrr->fixed4k[num - MSR_MTRR4kBase];  in vm_rdmtrr()
679 		*val = mtrr->fixed16k[num - MSR_MTRR16kBase];  in vm_rdmtrr()
682 		*val = mtrr->fixed64k;  in vm_rdmtrr()
684 	case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {  in vm_rdmtrr()
685 		u_int offset = num - MSR_MTRRVarBase;  in vm_rdmtrr()
687 			*val = mtrr->var[offset / 2].base;  in vm_rdmtrr()
689 			*val = mtrr->var[offset / 2].mask;  in vm_rdmtrr()
694 		return (-1);  in vm_rdmtrr()
706 		return (-1);  in vm_wrmtrr()
710 			return (-1);  in vm_wrmtrr()
712 		mtrr->def_type = val;  in vm_wrmtrr()
715 		mtrr->fixed4k[num - MSR_MTRR4kBase] = val;  in vm_wrmtrr()
718 		mtrr->fixed16k[num - MSR_MTRR16kBase] = val;  in vm_wrmtrr()
721 		mtrr->fixed64k = val;  in vm_wrmtrr()
723 	case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {  in vm_wrmtrr()
724 		u_int offset = num - MSR_MTRRVarBase;  in vm_wrmtrr()
728 				return (-1);  in vm_wrmtrr()
730 			mtrr->var[offset / 2].base = val;  in vm_wrmtrr()
734 				return (-1);  in vm_wrmtrr()
736 			mtrr->var[offset / 2].mask = val;  in vm_wrmtrr()
741 		return (-1);  in vm_wrmtrr()