Lines Matching +full:gpa +full:- +full:0
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
70 VIE_OP_TYPE_NONE = 0,
93 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
94 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
95 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
100 [0xF7] = {
101 .op_byte = 0xF7,
107 [0xAE] = {
108 .op_byte = 0xAE,
111 [0xB6] = {
112 .op_byte = 0xB6,
115 [0xB7] = {
116 .op_byte = 0xB7,
119 [0xBA] = {
120 .op_byte = 0xBA,
124 [0xBE] = {
125 .op_byte = 0xBE,
131 [0x03] = {
132 .op_byte = 0x03,
135 [0x0F] = {
136 .op_byte = 0x0F,
139 [0x0B] = {
140 .op_byte = 0x0B,
143 [0x2B] = {
144 .op_byte = 0x2B,
147 [0x39] = {
148 .op_byte = 0x39,
151 [0x3B] = {
152 .op_byte = 0x3B,
155 [0x88] = {
156 .op_byte = 0x88,
159 [0x89] = {
160 .op_byte = 0x89,
163 [0x8A] = {
164 .op_byte = 0x8A,
167 [0x8B] = {
168 .op_byte = 0x8B,
171 [0xA1] = {
172 .op_byte = 0xA1,
176 [0xA3] = {
177 .op_byte = 0xA3,
181 [0xA4] = {
182 .op_byte = 0xA4,
186 [0xA5] = {
187 .op_byte = 0xA5,
191 [0xAA] = {
192 .op_byte = 0xAA,
196 [0xAB] = {
197 .op_byte = 0xAB,
201 [0xC6] = {
202 /* XXX Group 11 extended opcode - not just MOV */
203 .op_byte = 0xC6,
207 [0xC7] = {
208 .op_byte = 0xC7,
212 [0x23] = {
213 .op_byte = 0x23,
216 [0x80] = {
218 .op_byte = 0x80,
222 [0x81] = {
224 .op_byte = 0x81,
228 [0x83] = {
230 .op_byte = 0x83,
234 [0x8F] = {
235 /* XXX Group 1A extended opcode - not just POP */
236 .op_byte = 0x8F,
239 [0xF6] = {
240 /* XXX Group 3 extended opcode - not just TEST */
241 .op_byte = 0xF6,
245 [0xF7] = {
246 /* XXX Group 3 extended opcode - not just TEST */
247 .op_byte = 0xF7,
251 [0xFF] = {
252 /* XXX Group 5 extended opcode - not just PUSH */
253 .op_byte = 0xFF,
259 #define VIE_MOD_INDIRECT 0
290 [1] = 0xff,
291 [2] = 0xffff,
292 [4] = 0xffffffff,
293 [8] = 0xffffffffffffffff,
309 *lhbr = 0; in vie_calc_bytereg()
310 *reg = gpr_map[vie->reg]; in vie_calc_bytereg()
313 * 64-bit mode imposes limitations on accessing legacy high byte in vie_calc_bytereg()
316 * The legacy high-byte registers cannot be addressed if the REX in vie_calc_bytereg()
321 * of the 'ModRM:reg' field address the legacy high-byte registers, in vie_calc_bytereg()
324 if (!vie->rex_present) { in vie_calc_bytereg()
325 if (vie->reg & 0x4) { in vie_calc_bytereg()
327 *reg = gpr_map[vie->reg & 0x3]; in vie_calc_bytereg()
362 if (error == 0) { in vie_write_bytereg()
364 mask = 0xff; in vie_write_bytereg()
396 val &= 0xffffffffUL; in vie_update_register()
411 * Return the status flags that would result from doing (x - y).
419 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
454 __asm __volatile("add %2,%1; pushfq; popq %0" : \
489 __asm __volatile("and %2,%1; pushfq; popq %0" : \
516 emulate_mov(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_mov() argument
524 size = vie->opsize; in emulate_mov()
527 switch (vie->op.op_byte) { in emulate_mov()
528 case 0x88: in emulate_mov()
536 if (error == 0) in emulate_mov()
537 error = memwrite(vcpu, gpa, byte, size, arg); in emulate_mov()
539 case 0x89: in emulate_mov()
546 reg = gpr_map[vie->reg]; in emulate_mov()
548 if (error == 0) { in emulate_mov()
550 error = memwrite(vcpu, gpa, val, size, arg); in emulate_mov()
553 case 0x8A: in emulate_mov()
560 error = memread(vcpu, gpa, &val, size, arg); in emulate_mov()
561 if (error == 0) in emulate_mov()
564 case 0x8B: in emulate_mov()
571 error = memread(vcpu, gpa, &val, size, arg); in emulate_mov()
572 if (error == 0) { in emulate_mov()
573 reg = gpr_map[vie->reg]; in emulate_mov()
577 case 0xA1: in emulate_mov()
584 error = memread(vcpu, gpa, &val, size, arg); in emulate_mov()
585 if (error == 0) { in emulate_mov()
590 case 0xA3: in emulate_mov()
598 if (error == 0) { in emulate_mov()
600 error = memwrite(vcpu, gpa, val, size, arg); in emulate_mov()
603 case 0xC6: in emulate_mov()
606 * C6/0 mov r/m8, imm8 in emulate_mov()
607 * REX + C6/0 mov r/m8, imm8 in emulate_mov()
610 error = memwrite(vcpu, gpa, vie->immediate, size, arg); in emulate_mov()
612 case 0xC7: in emulate_mov()
615 * C7/0 mov r/m16, imm16 in emulate_mov()
616 * C7/0 mov r/m32, imm32 in emulate_mov()
617 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits) in emulate_mov()
619 val = vie->immediate & size2mask[size]; in emulate_mov()
620 error = memwrite(vcpu, gpa, val, size, arg); in emulate_mov()
630 emulate_movx(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_movx() argument
637 size = vie->opsize; in emulate_movx()
640 switch (vie->op.op_byte) { in emulate_movx()
641 case 0xB6: in emulate_movx()
646 * 0F B6/r movzx r16, r/m8 in emulate_movx()
647 * 0F B6/r movzx r32, r/m8 in emulate_movx()
648 * REX.W + 0F B6/r movzx r64, r/m8 in emulate_movx()
652 error = memread(vcpu, gpa, &val, 1, arg); in emulate_movx()
657 reg = gpr_map[vie->reg]; in emulate_movx()
659 /* zero-extend byte */ in emulate_movx()
665 case 0xB7: in emulate_movx()
670 * 0F B7/r movzx r32, r/m16 in emulate_movx()
671 * REX.W + 0F B7/r movzx r64, r/m16 in emulate_movx()
673 error = memread(vcpu, gpa, &val, 2, arg); in emulate_movx()
677 reg = gpr_map[vie->reg]; in emulate_movx()
679 /* zero-extend word */ in emulate_movx()
684 case 0xBE: in emulate_movx()
689 * 0F BE/r movsx r16, r/m8 in emulate_movx()
690 * 0F BE/r movsx r32, r/m8 in emulate_movx()
691 * REX.W + 0F BE/r movsx r64, r/m8 in emulate_movx()
695 error = memread(vcpu, gpa, &val, 1, arg); in emulate_movx()
700 reg = gpr_map[vie->reg]; in emulate_movx()
727 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error)); in get_gla()
730 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in get_gla()
733 KASSERT(error == 0, ("%s: error %d getting segment descriptor %d", in get_gla()
737 KASSERT(error == 0, ("%s: error %d getting register %d", __func__, in get_gla()
740 if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize, in get_gla()
743 vm_inject_ss(vcpu, 0); in get_gla()
749 if (vie_canonical_check(paging->cpu_mode, *gla)) { in get_gla()
751 vm_inject_ss(vcpu, 0); in get_gla()
757 if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) { in get_gla()
758 vm_inject_ac(vcpu, 0); in get_gla()
762 *fault = 0; in get_gla()
763 return (0); in get_gla()
767 return (0); in get_gla()
771 emulate_movs(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_movs() argument
784 opsize = (vie->op.op_byte == 0xA4) ? 1 : vie->opsize; in emulate_movs()
785 val = 0; in emulate_movs()
786 error = 0; in emulate_movs()
795 repeat = vie->repz_present | vie->repnz_present; in emulate_movs()
805 if ((rcx & vie_size2mask(vie->addrsize)) == 0) { in emulate_movs()
806 error = 0; in emulate_movs()
813 * -------------------------------------------- in emulate_movs()
823 * XXX the emulation doesn't properly handle the case where 'gpa' in emulate_movs()
827 seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS; in emulate_movs()
828 error = get_gla(vcpu, vie, paging, opsize, vie->addrsize, in emulate_movs()
835 if (error == 0) { in emulate_movs()
844 error = memwrite(vcpu, gpa, val, opsize, arg); in emulate_movs()
853 error = get_gla(vcpu, vie, paging, opsize, vie->addrsize, in emulate_movs()
861 if (error == 0) { in emulate_movs()
868 * A MMIO read can have side-effects so we in emulate_movs()
870 * successful. If a page-fault needs to be in emulate_movs()
874 error = memread(vcpu, gpa, &val, opsize, arg); in emulate_movs()
885 * side-effects) only after we are sure that the in emulate_movs()
910 KASSERT(error == 0, ("%s: error %d getting rsi", __func__, error)); in emulate_movs()
913 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error)); in emulate_movs()
916 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_movs()
919 rsi -= opsize; in emulate_movs()
920 rdi -= opsize; in emulate_movs()
927 vie->addrsize); in emulate_movs()
928 KASSERT(error == 0, ("%s: error %d updating rsi", __func__, error)); in emulate_movs()
931 vie->addrsize); in emulate_movs()
932 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error)); in emulate_movs()
935 rcx = rcx - 1; in emulate_movs()
937 rcx, vie->addrsize); in emulate_movs()
943 if ((rcx & vie_size2mask(vie->addrsize)) != 0) in emulate_movs()
947 KASSERT(error == 0 || error == EFAULT, ("%s: unexpected error %d", in emulate_movs()
953 emulate_stos(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_stos() argument
961 opsize = (vie->op.op_byte == 0xAA) ? 1 : vie->opsize; in emulate_stos()
962 repeat = vie->repz_present | vie->repnz_present; in emulate_stos()
972 if ((rcx & vie_size2mask(vie->addrsize)) == 0) in emulate_stos()
973 return (0); in emulate_stos()
979 error = memwrite(vcpu, gpa, val, opsize, arg); in emulate_stos()
984 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error)); in emulate_stos()
987 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_stos()
990 rdi -= opsize; in emulate_stos()
995 vie->addrsize); in emulate_stos()
996 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error)); in emulate_stos()
999 rcx = rcx - 1; in emulate_stos()
1001 rcx, vie->addrsize); in emulate_stos()
1007 if ((rcx & vie_size2mask(vie->addrsize)) != 0) in emulate_stos()
1011 return (0); in emulate_stos()
1015 emulate_and(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_and() argument
1022 size = vie->opsize; in emulate_and()
1025 switch (vie->op.op_byte) { in emulate_and()
1026 case 0x23: in emulate_and()
1037 reg = gpr_map[vie->reg]; in emulate_and()
1043 error = memread(vcpu, gpa, &val2, size, arg); in emulate_and()
1051 case 0x81: in emulate_and()
1052 case 0x83: in emulate_and()
1059 * REX.W + 81 /4 and r/m64, imm32 sign-extended to 64 in emulate_and()
1061 * 83 /4 and r/m16, imm8 sign-extended to 16 in emulate_and()
1062 * 83 /4 and r/m32, imm8 sign-extended to 32 in emulate_and()
1063 * REX.W + 83/4 and r/m64, imm8 sign-extended to 64 in emulate_and()
1067 error = memread(vcpu, gpa, &val1, size, arg); in emulate_and()
1072 * perform the operation with the pre-fetched immediate in emulate_and()
1075 result = val1 & vie->immediate; in emulate_and()
1076 error = memwrite(vcpu, gpa, result, size, arg); in emulate_and()
1092 * The updated status flags are obtained by subtracting 0 from 'result'. in emulate_and()
1094 rflags2 = getcc(size, result, 0); in emulate_and()
1103 emulate_or(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_or() argument
1110 size = vie->opsize; in emulate_or()
1113 switch (vie->op.op_byte) { in emulate_or()
1114 case 0x0B: in emulate_or()
1119 * 0b/r or r16, r/m16 in emulate_or()
1120 * 0b/r or r32, r/m32 in emulate_or()
1121 * REX.W + 0b/r or r64, r/m64 in emulate_or()
1125 reg = gpr_map[vie->reg]; in emulate_or()
1131 error = memread(vcpu, gpa, &val2, size, arg); in emulate_or()
1139 case 0x81: in emulate_or()
1140 case 0x83: in emulate_or()
1147 * REX.W + 81 /1 or r/m64, imm32 sign-extended to 64 in emulate_or()
1149 * 83 /1 or r/m16, imm8 sign-extended to 16 in emulate_or()
1150 * 83 /1 or r/m32, imm8 sign-extended to 32 in emulate_or()
1151 * REX.W + 83/1 or r/m64, imm8 sign-extended to 64 in emulate_or()
1155 error = memread(vcpu, gpa, &val1, size, arg); in emulate_or()
1160 * perform the operation with the pre-fetched immediate in emulate_or()
1163 result = val1 | vie->immediate; in emulate_or()
1164 error = memwrite(vcpu, gpa, result, size, arg); in emulate_or()
1180 * The updated status flags are obtained by subtracting 0 from 'result'. in emulate_or()
1182 rflags2 = getcc(size, result, 0); in emulate_or()
1191 emulate_cmp(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_cmp() argument
1198 size = vie->opsize; in emulate_cmp()
1199 switch (vie->op.op_byte) { in emulate_cmp()
1200 case 0x39: in emulate_cmp()
1201 case 0x3B: in emulate_cmp()
1218 reg = gpr_map[vie->reg]; in emulate_cmp()
1224 error = memread(vcpu, gpa, &memop, size, arg); in emulate_cmp()
1228 if (vie->op.op_byte == 0x3B) { in emulate_cmp()
1237 case 0x80: in emulate_cmp()
1238 case 0x81: in emulate_cmp()
1239 case 0x83: in emulate_cmp()
1246 * REX.W + 81 /7 cmp r/m64, imm32 sign-extended to 64 in emulate_cmp()
1248 * 83 /7 cmp r/m16, imm8 sign-extended to 16 in emulate_cmp()
1249 * 83 /7 cmp r/m32, imm8 sign-extended to 32 in emulate_cmp()
1250 * REX.W + 83 /7 cmp r/m64, imm8 sign-extended to 64 in emulate_cmp()
1259 if (vie->op.op_byte == 0x80) in emulate_cmp()
1263 error = memread(vcpu, gpa, &op1, size, arg); in emulate_cmp()
1267 rflags2 = getcc(size, op1, vie->immediate); in emulate_cmp()
1283 emulate_test(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_test() argument
1289 size = vie->opsize; in emulate_test()
1292 switch (vie->op.op_byte) { in emulate_test()
1293 case 0xF6: in emulate_test()
1295 * F6 /0 test r/m8, imm8 in emulate_test()
1299 case 0xF7: in emulate_test()
1301 * F7 /0 test r/m16, imm16 in emulate_test()
1302 * F7 /0 test r/m32, imm32 in emulate_test()
1303 * REX.W + F7 /0 test r/m64, imm32 sign-extended to 64 in emulate_test()
1310 if ((vie->reg & 7) != 0) in emulate_test()
1313 error = memread(vcpu, gpa, &op1, size, arg); in emulate_test()
1317 rflags2 = getandflags(size, op1, vie->immediate); in emulate_test()
1338 emulate_bextr(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_bextr() argument
1346 size = vie->opsize; in emulate_bextr()
1350 * VEX.LZ.0F38.W0 F7 /r BEXTR r32a, r/m32, r32b in emulate_bextr()
1351 * VEX.LZ.0F38.W1 F7 /r BEXTR r64a, r/m64, r64b in emulate_bextr()
1356 * Operand size is always 32-bit if not in 64-bit mode (W1 is ignored). in emulate_bextr()
1358 if (size != 4 && paging->cpu_mode != CPU_MODE_64BIT) in emulate_bextr()
1366 error = memread(vcpu, gpa, &src1, size, arg); in emulate_bextr()
1369 error = vie_read_register(vcpu, gpr_map[vie->vex_reg], &src2); in emulate_bextr()
1376 start = (src2 & 0xff); in emulate_bextr()
1377 len = (src2 & 0xff00) >> 8; in emulate_bextr()
1380 dst = 0; in emulate_bextr()
1387 len = (size * 8) - start; in emulate_bextr()
1388 if (len == 0) in emulate_bextr()
1391 if (start > 0) in emulate_bextr()
1394 src1 = src1 & ((1ull << len) - 1); in emulate_bextr()
1398 error = vie_update_register(vcpu, gpr_map[vie->reg], dst, size); in emulate_bextr()
1407 if (dst == 0) in emulate_bextr()
1415 emulate_add(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_add() argument
1422 size = vie->opsize; in emulate_add()
1425 switch (vie->op.op_byte) { in emulate_add()
1426 case 0x03: in emulate_add()
1436 reg = gpr_map[vie->reg]; in emulate_add()
1442 error = memread(vcpu, gpa, &val2, size, arg); in emulate_add()
1471 emulate_sub(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_sub() argument
1478 size = vie->opsize; in emulate_sub()
1481 switch (vie->op.op_byte) { in emulate_sub()
1482 case 0x2B: in emulate_sub()
1492 reg = gpr_map[vie->reg]; in emulate_sub()
1498 error = memread(vcpu, gpa, &val2, size, arg); in emulate_sub()
1503 nval = val1 - val2; in emulate_sub()
1540 val = 0; in emulate_stack_op()
1541 size = vie->opsize; in emulate_stack_op()
1542 pushop = (vie->op.op_type == VIE_OP_TYPE_PUSH) ? 1 : 0; in emulate_stack_op()
1545 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1 in emulate_stack_op()
1547 if (paging->cpu_mode == CPU_MODE_REAL) { in emulate_stack_op()
1549 } else if (paging->cpu_mode == CPU_MODE_64BIT) { in emulate_stack_op()
1551 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3 in emulate_stack_op()
1552 * - Stack pointer size is always 64-bits. in emulate_stack_op()
1553 * - PUSH/POP of 32-bit values is not possible in 64-bit mode. in emulate_stack_op()
1554 * - 16-bit PUSH/POP is supported by using the operand size in emulate_stack_op()
1558 size = vie->opsize_override ? 2 : 8; in emulate_stack_op()
1562 * stack-segment descriptor determines the size of the in emulate_stack_op()
1566 KASSERT(error == 0, ("%s: error %d getting SS descriptor", in emulate_stack_op()
1575 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error)); in emulate_stack_op()
1578 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_stack_op()
1581 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error)); in emulate_stack_op()
1583 rsp -= size; in emulate_stack_op()
1586 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc, in emulate_stack_op()
1589 vm_inject_ss(vcpu, 0); in emulate_stack_op()
1590 return (0); in emulate_stack_op()
1593 if (vie_canonical_check(paging->cpu_mode, stack_gla)) { in emulate_stack_op()
1594 vm_inject_ss(vcpu, 0); in emulate_stack_op()
1595 return (0); in emulate_stack_op()
1598 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) { in emulate_stack_op()
1599 vm_inject_ac(vcpu, 0); in emulate_stack_op()
1600 return (0); in emulate_stack_op()
1611 if (error == 0) in emulate_stack_op()
1620 if (error == 0) { in emulate_stack_op()
1623 KASSERT(error == 0, ("error %d updating rsp", error)); in emulate_stack_op()
1636 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2. in emulate_push()
1641 if ((vie->reg & 7) != 6) in emulate_push()
1657 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2. in emulate_pop()
1662 if ((vie->reg & 7) != 0) in emulate_pop()
1671 emulate_group1(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_group1() argument
1677 switch (vie->reg & 7) { in emulate_group1()
1678 case 0x1: /* OR */ in emulate_group1()
1679 error = emulate_or(vcpu, gpa, vie, in emulate_group1()
1682 case 0x4: /* AND */ in emulate_group1()
1683 error = emulate_and(vcpu, gpa, vie, in emulate_group1()
1686 case 0x7: /* CMP */ in emulate_group1()
1687 error = emulate_cmp(vcpu, gpa, vie, in emulate_group1()
1699 emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_bittest() argument
1707 * 0F BA is a Group 8 extended opcode. in emulate_bittest()
1712 if ((vie->reg & 7) != 4) in emulate_bittest()
1716 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_bittest()
1718 error = memread(vcpu, gpa, &val, vie->opsize, memarg); in emulate_bittest()
1723 * Intel SDM, Vol 2, Table 3-2: in emulate_bittest()
1726 bitmask = vie->opsize * 8 - 1; in emulate_bittest()
1727 bitoff = vie->immediate & bitmask; in emulate_bittest()
1736 KASSERT(error == 0, ("%s: error %d updating rflags", __func__, error)); in emulate_bittest()
1738 return (0); in emulate_bittest()
1742 emulate_twob_group15(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_twob_group15() argument
1749 switch (vie->reg & 7) { in emulate_twob_group15()
1750 case 0x7: /* CLFLUSH, CLFLUSHOPT, and SFENCE */ in emulate_twob_group15()
1751 if (vie->mod == 0x3) { in emulate_twob_group15()
1756 error = 0; in emulate_twob_group15()
1762 error = memread(vcpu, gpa, &buf, 1, memarg); in emulate_twob_group15()
1774 vmm_emulate_instruction(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in vmm_emulate_instruction() argument
1780 if (!vie->decoded) in vmm_emulate_instruction()
1783 switch (vie->op.op_type) { in vmm_emulate_instruction()
1785 error = emulate_group1(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1789 error = emulate_pop(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1793 error = emulate_push(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1797 error = emulate_cmp(vcpu, gpa, vie, in vmm_emulate_instruction()
1801 error = emulate_mov(vcpu, gpa, vie, in vmm_emulate_instruction()
1806 error = emulate_movx(vcpu, gpa, vie, in vmm_emulate_instruction()
1810 error = emulate_movs(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1814 error = emulate_stos(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1818 error = emulate_and(vcpu, gpa, vie, in vmm_emulate_instruction()
1822 error = emulate_or(vcpu, gpa, vie, in vmm_emulate_instruction()
1826 error = emulate_sub(vcpu, gpa, vie, in vmm_emulate_instruction()
1830 error = emulate_bittest(vcpu, gpa, vie, in vmm_emulate_instruction()
1834 error = emulate_twob_group15(vcpu, gpa, vie, in vmm_emulate_instruction()
1838 error = emulate_add(vcpu, gpa, vie, memread, in vmm_emulate_instruction()
1842 error = emulate_test(vcpu, gpa, vie, in vmm_emulate_instruction()
1846 error = emulate_bextr(vcpu, gpa, vie, paging, in vmm_emulate_instruction()
1862 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl)); in vie_alignment_check()
1864 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0) in vie_alignment_check()
1865 return (0); in vie_alignment_check()
1867 return ((gla & (size - 1)) ? 1 : 0); in vie_alignment_check()
1876 return (0); in vie_canonical_check()
1882 mask = ~((1UL << 48) - 1); in vie_canonical_check()
1886 return ((gla & mask) != 0); in vie_canonical_check()
1909 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0, in vie_calculate_gla()
1924 * it results in a #GP(0). in vie_calculate_gla()
1926 if (SEG_DESC_UNUSABLE(desc->access)) in vie_calculate_gla()
1927 return (-1); in vie_calculate_gla()
1933 * it would have been checked before the VM-exit. in vie_calculate_gla()
1935 KASSERT(SEG_DESC_PRESENT(desc->access), in vie_calculate_gla()
1936 ("segment %d not present: %#x", seg, desc->access)); in vie_calculate_gla()
1941 type = SEG_DESC_TYPE(desc->access); in vie_calculate_gla()
1946 /* #GP on a read access to a exec-only code segment */ in vie_calculate_gla()
1947 if ((type & 0xA) == 0x8) in vie_calculate_gla()
1948 return (-1); in vie_calculate_gla()
1954 * read-only data segment. in vie_calculate_gla()
1956 if (type & 0x8) /* code segment */ in vie_calculate_gla()
1957 return (-1); in vie_calculate_gla()
1959 if ((type & 0xA) == 0) /* read-only data seg */ in vie_calculate_gla()
1960 return (-1); in vie_calculate_gla()
1964 * 'desc->limit' is fully expanded taking granularity into in vie_calculate_gla()
1967 if ((type & 0xC) == 0x4) { in vie_calculate_gla()
1968 /* expand-down data segment */ in vie_calculate_gla()
1969 low_limit = desc->limit + 1; in vie_calculate_gla()
1970 high_limit = SEG_DESC_DEF32(desc->access) ? in vie_calculate_gla()
1971 0xffffffff : 0xffff; in vie_calculate_gla()
1973 /* code segment or expand-up data segment */ in vie_calculate_gla()
1974 low_limit = 0; in vie_calculate_gla()
1975 high_limit = desc->limit; in vie_calculate_gla()
1978 while (length > 0) { in vie_calculate_gla()
1981 return (-1); in vie_calculate_gla()
1983 length--; in vie_calculate_gla()
1988 * In 64-bit mode all segments except %fs and %gs have a segment in vie_calculate_gla()
1989 * base address of 0. in vie_calculate_gla()
1993 segbase = 0; in vie_calculate_gla()
1995 segbase = desc->base; in vie_calculate_gla()
2004 return (0); in vie_calculate_gla()
2018 memset((char *)vie + offsetof(struct vie, vie_startzero), 0, in vie_restart()
2019 sizeof(*vie) - offsetof(struct vie, vie_startzero)); in vie_restart()
2021 vie->base_register = VM_REG_LAST; in vie_restart()
2022 vie->index_register = VM_REG_LAST; in vie_restart()
2023 vie->segment_register = VM_REG_LAST; in vie_restart()
2029 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE, in vie_init()
2033 memset(vie->inst, 0, sizeof(vie->inst)); in vie_init()
2034 if (inst_length != 0) in vie_init()
2035 memcpy(vie->inst, inst_bytes, inst_length); in vie_init()
2036 vie->num_valid = inst_length; in vie_init()
2043 int error_code = 0; in pf_error_code()
2080 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault, bool check_only) in _vm_gla2gpa() argument
2088 *guest_fault = 0; in _vm_gla2gpa()
2090 usermode = (paging->cpl == 3 ? 1 : 0); in _vm_gla2gpa()
2093 retval = 0; in _vm_gla2gpa()
2094 retries = 0; in _vm_gla2gpa()
2096 ptpphys = paging->cr3; /* root of the page tables */ in _vm_gla2gpa()
2098 if (retries++ > 0) in _vm_gla2gpa()
2101 if (vie_canonical_check(paging->cpu_mode, gla)) { in _vm_gla2gpa()
2103 * XXX assuming a non-stack reference otherwise a stack fault in _vm_gla2gpa()
2111 if (paging->paging_mode == PAGING_MODE_FLAT) { in _vm_gla2gpa()
2112 *gpa = gla; in _vm_gla2gpa()
2116 if (paging->paging_mode == PAGING_MODE_32) { in _vm_gla2gpa()
2118 while (--nlevels >= 0) { in _vm_gla2gpa()
2120 ptpphys &= ~0xfff; in _vm_gla2gpa()
2129 ptpindex = (gla >> ptpshift) & 0x3FF; in _vm_gla2gpa()
2134 if ((pte32 & PG_V) == 0 || in _vm_gla2gpa()
2135 (usermode && (pte32 & PG_U) == 0) || in _vm_gla2gpa()
2136 (writable && (pte32 & PG_RW) == 0)) { in _vm_gla2gpa()
2138 pfcode = pf_error_code(usermode, prot, 0, in _vm_gla2gpa()
2152 if (!check_only && (pte32 & PG_A) == 0) { in _vm_gla2gpa()
2154 pte32, pte32 | PG_A) == 0) { in _vm_gla2gpa()
2159 /* XXX must be ignored if CR4.PSE=0 */ in _vm_gla2gpa()
2160 if (nlevels > 0 && (pte32 & PG_PS) != 0) in _vm_gla2gpa()
2167 if (!check_only && writable && (pte32 & PG_M) == 0) { in _vm_gla2gpa()
2169 pte32, pte32 | PG_M) == 0) { in _vm_gla2gpa()
2176 *gpa = pte32 | (gla & (pgsize - 1)); in _vm_gla2gpa()
2180 if (paging->paging_mode == PAGING_MODE_PAE) { in _vm_gla2gpa()
2182 ptpphys &= 0xffffffe0UL; in _vm_gla2gpa()
2189 ptpindex = (gla >> 30) & 0x3; in _vm_gla2gpa()
2193 if ((pte & PG_V) == 0) { in _vm_gla2gpa()
2195 pfcode = pf_error_code(usermode, prot, 0, pte); in _vm_gla2gpa()
2204 } else if (paging->paging_mode == PAGING_MODE_64_LA57) { in _vm_gla2gpa()
2210 while (--nlevels >= 0) { in _vm_gla2gpa()
2219 ptpindex = (gla >> ptpshift) & 0x1FF; in _vm_gla2gpa()
2224 if ((pte & PG_V) == 0 || in _vm_gla2gpa()
2225 (usermode && (pte & PG_U) == 0) || in _vm_gla2gpa()
2226 (writable && (pte & PG_RW) == 0)) { in _vm_gla2gpa()
2228 pfcode = pf_error_code(usermode, prot, 0, pte); in _vm_gla2gpa()
2235 if (!check_only && (pte & PG_A) == 0) { in _vm_gla2gpa()
2237 pte, pte | PG_A) == 0) { in _vm_gla2gpa()
2242 if (nlevels > 0 && (pte & PG_PS) != 0) { in _vm_gla2gpa()
2258 if (!check_only && writable && (pte & PG_M) == 0) { in _vm_gla2gpa()
2259 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0) in _vm_gla2gpa()
2265 *gpa = pte | (gla & (pgsize - 1)); in _vm_gla2gpa()
2268 KASSERT(retval == 0 || retval == EFAULT, ("%s: unexpected retval %d", in _vm_gla2gpa()
2281 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault) in vm_gla2gpa() argument
2284 return (_vm_gla2gpa(vcpu, paging, gla, prot, gpa, guest_fault, in vm_gla2gpa()
2290 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault) in vm_gla2gpa_nofault() argument
2293 return (_vm_gla2gpa(vcpu, paging, gla, prot, gpa, guest_fault, in vm_gla2gpa_nofault()
2313 vm_copyin(copyinfo, vie->inst, inst_length); in vmm_fetch_instruction()
2315 vie->num_valid = inst_length; in vmm_fetch_instruction()
2316 return (0); in vmm_fetch_instruction()
2324 if (vie->num_processed < vie->num_valid) { in vie_peek()
2325 *x = vie->inst[vie->num_processed]; in vie_peek()
2326 return (0); in vie_peek()
2328 return (-1); in vie_peek()
2335 vie->num_processed++; in vie_advance()
2343 case 0x2E: in segment_override()
2346 case 0x36: in segment_override()
2349 case 0x3E: in segment_override()
2352 case 0x26: in segment_override()
2355 case 0x64: in segment_override()
2358 case 0x65: in segment_override()
2374 return (-1); in decode_prefixes()
2376 if (x == 0x66) in decode_prefixes()
2377 vie->opsize_override = 1; in decode_prefixes()
2378 else if (x == 0x67) in decode_prefixes()
2379 vie->addrsize_override = 1; in decode_prefixes()
2380 else if (x == 0xF3) in decode_prefixes()
2381 vie->repz_present = 1; in decode_prefixes()
2382 else if (x == 0xF2) in decode_prefixes()
2383 vie->repnz_present = 1; in decode_prefixes()
2384 else if (segment_override(x, &vie->segment_register)) in decode_prefixes()
2385 vie->segment_override = 1; in decode_prefixes()
2394 * - Only one REX prefix is allowed per instruction. in decode_prefixes()
2395 * - The REX prefix must immediately precede the opcode byte or the in decode_prefixes()
2397 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3) in decode_prefixes()
2400 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) { in decode_prefixes()
2401 vie->rex_present = 1; in decode_prefixes()
2402 vie->rex_w = x & 0x8 ? 1 : 0; in decode_prefixes()
2403 vie->rex_r = x & 0x4 ? 1 : 0; in decode_prefixes()
2404 vie->rex_x = x & 0x2 ? 1 : 0; in decode_prefixes()
2405 vie->rex_b = x & 0x1 ? 1 : 0; in decode_prefixes()
2413 && x == 0xC4) { in decode_prefixes()
2416 /* 3-byte VEX prefix. */ in decode_prefixes()
2417 vie->vex_present = 1; in decode_prefixes()
2421 return (-1); in decode_prefixes()
2424 * 2nd byte: [R', X', B', mmmmm[4:0]]. Bits are inverted in decode_prefixes()
2427 vie->rex_r = x & 0x80 ? 0 : 1; in decode_prefixes()
2428 vie->rex_x = x & 0x40 ? 0 : 1; in decode_prefixes()
2429 vie->rex_b = x & 0x20 ? 0 : 1; in decode_prefixes()
2431 switch (x & 0x1F) { in decode_prefixes()
2432 case 0x2: in decode_prefixes()
2433 /* 0F 38. */ in decode_prefixes()
2436 case 0x1: in decode_prefixes()
2437 /* 0F class - nothing handled here yet. */ in decode_prefixes()
2439 case 0x3: in decode_prefixes()
2440 /* 0F 3A class - nothing handled here yet. */ in decode_prefixes()
2444 return (-1); in decode_prefixes()
2449 return (-1); in decode_prefixes()
2451 /* 3rd byte: [W, vvvv[6:3], L, pp[1:0]]. */ in decode_prefixes()
2452 vie->rex_w = x & 0x80 ? 1 : 0; in decode_prefixes()
2454 vie->vex_reg = ((~(unsigned)x & 0x78u) >> 3); in decode_prefixes()
2455 vie->vex_l = !!(x & 0x4); in decode_prefixes()
2456 vie->vex_pp = (x & 0x3); in decode_prefixes()
2459 switch (vie->vex_pp) { in decode_prefixes()
2460 case 0x1: in decode_prefixes()
2461 vie->opsize_override = 1; in decode_prefixes()
2463 case 0x2: in decode_prefixes()
2464 vie->repz_present = 1; in decode_prefixes()
2466 case 0x3: in decode_prefixes()
2467 vie->repnz_present = 1; in decode_prefixes()
2475 return (-1); in decode_prefixes()
2477 vie->op = optab[x]; in decode_prefixes()
2478 if (vie->op.op_type == VIE_OP_TYPE_NONE) in decode_prefixes()
2479 return (-1); in decode_prefixes()
2485 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1 in decode_prefixes()
2489 * Default address size is 64-bits and default operand size in decode_prefixes()
2490 * is 32-bits. in decode_prefixes()
2492 vie->addrsize = vie->addrsize_override ? 4 : 8; in decode_prefixes()
2493 if (vie->rex_w) in decode_prefixes()
2494 vie->opsize = 8; in decode_prefixes()
2495 else if (vie->opsize_override) in decode_prefixes()
2496 vie->opsize = 2; in decode_prefixes()
2498 vie->opsize = 4; in decode_prefixes()
2500 /* Default address and operand sizes are 32-bits */ in decode_prefixes()
2501 vie->addrsize = vie->addrsize_override ? 2 : 4; in decode_prefixes()
2502 vie->opsize = vie->opsize_override ? 2 : 4; in decode_prefixes()
2504 /* Default address and operand sizes are 16-bits */ in decode_prefixes()
2505 vie->addrsize = vie->addrsize_override ? 4 : 2; in decode_prefixes()
2506 vie->opsize = vie->opsize_override ? 4 : 2; in decode_prefixes()
2508 return (0); in decode_prefixes()
2517 return (-1); in decode_two_byte_opcode()
2519 vie->op = two_byte_opcodes[x]; in decode_two_byte_opcode()
2521 if (vie->op.op_type == VIE_OP_TYPE_NONE) in decode_two_byte_opcode()
2522 return (-1); in decode_two_byte_opcode()
2525 return (0); in decode_two_byte_opcode()
2534 return (-1); in decode_opcode()
2537 if (vie->op.op_type != VIE_OP_TYPE_NONE) in decode_opcode()
2538 return (0); in decode_opcode()
2540 vie->op = one_byte_opcodes[x]; in decode_opcode()
2542 if (vie->op.op_type == VIE_OP_TYPE_NONE) in decode_opcode()
2543 return (-1); in decode_opcode()
2547 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE) in decode_opcode()
2550 return (0); in decode_opcode()
2558 if (vie->op.op_flags & VIE_OP_F_NO_MODRM) in decode_modrm()
2559 return (0); in decode_modrm()
2562 return (-1); in decode_modrm()
2565 return (-1); in decode_modrm()
2567 vie->mod = (x >> 6) & 0x3; in decode_modrm()
2568 vie->rm = (x >> 0) & 0x7; in decode_modrm()
2569 vie->reg = (x >> 3) & 0x7; in decode_modrm()
2576 if (vie->mod == VIE_MOD_DIRECT) in decode_modrm()
2577 return (-1); in decode_modrm()
2579 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) || in decode_modrm()
2580 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) { in decode_modrm()
2582 * Table 2-5: Special Cases of REX Encodings in decode_modrm()
2584 * mod=0, r/m=5 is used in the compatibility mode to in decode_modrm()
2594 vie->rm |= (vie->rex_b << 3); in decode_modrm()
2597 vie->reg |= (vie->rex_r << 3); in decode_modrm()
2600 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB) in decode_modrm()
2603 vie->base_register = gpr_map[vie->rm]; in decode_modrm()
2605 switch (vie->mod) { in decode_modrm()
2607 vie->disp_bytes = 1; in decode_modrm()
2610 vie->disp_bytes = 4; in decode_modrm()
2613 if (vie->rm == VIE_RM_DISP32) { in decode_modrm()
2614 vie->disp_bytes = 4; in decode_modrm()
2616 * Table 2-7. RIP-Relative Addressing in decode_modrm()
2618 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32 in decode_modrm()
2623 vie->base_register = VM_REG_GUEST_RIP; in decode_modrm()
2625 vie->base_register = VM_REG_LAST; in decode_modrm()
2633 return (0); in decode_modrm()
2642 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB) in decode_sib()
2643 return (0); in decode_sib()
2646 return (-1); in decode_sib()
2648 /* De-construct the SIB byte */ in decode_sib()
2649 vie->ss = (x >> 6) & 0x3; in decode_sib()
2650 vie->index = (x >> 3) & 0x7; in decode_sib()
2651 vie->base = (x >> 0) & 0x7; in decode_sib()
2654 vie->index |= vie->rex_x << 3; in decode_sib()
2655 vie->base |= vie->rex_b << 3; in decode_sib()
2657 switch (vie->mod) { in decode_sib()
2659 vie->disp_bytes = 1; in decode_sib()
2662 vie->disp_bytes = 4; in decode_sib()
2666 if (vie->mod == VIE_MOD_INDIRECT && in decode_sib()
2667 (vie->base == 5 || vie->base == 13)) { in decode_sib()
2669 * Special case when base register is unused if mod = 0 in decode_sib()
2673 * Table 2-3: 32-bit Addressing Forms with the SIB Byte in decode_sib()
2674 * Table 2-5: Special Cases of REX Encodings in decode_sib()
2676 vie->disp_bytes = 4; in decode_sib()
2678 vie->base_register = gpr_map[vie->base]; in decode_sib()
2685 * Table 2-3: 32-bit Addressing Forms with the SIB Byte in decode_sib()
2686 * Table 2-5: Special Cases of REX Encodings in decode_sib()
2688 if (vie->index != 4) in decode_sib()
2689 vie->index_register = gpr_map[vie->index]; in decode_sib()
2692 if (vie->index_register < VM_REG_LAST) in decode_sib()
2693 vie->scale = 1 << vie->ss; in decode_sib()
2697 return (0); in decode_sib()
2712 if ((n = vie->disp_bytes) == 0) in decode_displacement()
2713 return (0); in decode_displacement()
2718 for (i = 0; i < n; i++) { in decode_displacement()
2720 return (-1); in decode_displacement()
2727 vie->displacement = u.signed8; /* sign-extended */ in decode_displacement()
2729 vie->displacement = u.signed32; /* sign-extended */ in decode_displacement()
2731 return (0); in decode_displacement()
2747 if (vie->op.op_flags & VIE_OP_F_IMM) { in decode_immediate()
2750 * In 64-bit mode the typical size of immediate operands in decode_immediate()
2751 * remains 32-bits. When the operand size if 64-bits, the in decode_immediate()
2752 * processor sign-extends all immediates to 64-bits prior in decode_immediate()
2755 if (vie->opsize == 4 || vie->opsize == 8) in decode_immediate()
2756 vie->imm_bytes = 4; in decode_immediate()
2758 vie->imm_bytes = 2; in decode_immediate()
2759 } else if (vie->op.op_flags & VIE_OP_F_IMM8) { in decode_immediate()
2760 vie->imm_bytes = 1; in decode_immediate()
2763 if ((n = vie->imm_bytes) == 0) in decode_immediate()
2764 return (0); in decode_immediate()
2769 for (i = 0; i < n; i++) { in decode_immediate()
2771 return (-1); in decode_immediate()
2777 /* sign-extend the immediate value before use */ in decode_immediate()
2779 vie->immediate = u.signed8; in decode_immediate()
2781 vie->immediate = u.signed16; in decode_immediate()
2783 vie->immediate = u.signed32; in decode_immediate()
2785 return (0); in decode_immediate()
2798 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0) in decode_moffset()
2799 return (0); in decode_moffset()
2802 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM: in decode_moffset()
2803 * The memory offset size follows the address-size of the instruction. in decode_moffset()
2805 n = vie->addrsize; in decode_moffset()
2808 u.u64 = 0; in decode_moffset()
2809 for (i = 0; i < n; i++) { in decode_moffset()
2811 return (-1); in decode_moffset()
2816 vie->displacement = u.u64; in decode_moffset()
2817 return (0); in decode_moffset()
2836 return (0); in verify_gla()
2838 base = 0; in verify_gla()
2839 if (vie->base_register != VM_REG_LAST) { in verify_gla()
2840 error = vm_get_register(vcpu, vie->base_register, &base); in verify_gla()
2843 error, vie->base_register); in verify_gla()
2844 return (-1); in verify_gla()
2848 * RIP-relative addressing starts from the following in verify_gla()
2851 if (vie->base_register == VM_REG_GUEST_RIP) in verify_gla()
2852 base += vie->num_processed; in verify_gla()
2855 idx = 0; in verify_gla()
2856 if (vie->index_register != VM_REG_LAST) { in verify_gla()
2857 error = vm_get_register(vcpu, vie->index_register, &idx); in verify_gla()
2860 error, vie->index_register); in verify_gla()
2861 return (-1); in verify_gla()
2868 * In 64-bit mode, segmentation is generally (but not in verify_gla()
2872 * In legacy IA-32 mode, when the ESP or EBP register is used in verify_gla()
2878 if (vie->segment_override) in verify_gla()
2879 seg = vie->segment_register; in verify_gla()
2880 else if (vie->base_register == VM_REG_GUEST_RSP || in verify_gla()
2881 vie->base_register == VM_REG_GUEST_RBP) in verify_gla()
2887 segbase = 0; in verify_gla()
2893 vie->segment_register); in verify_gla()
2894 return (-1); in verify_gla()
2899 gla2 = segbase + base + vie->scale * idx + vie->displacement; in verify_gla()
2900 gla2 &= size2mask[vie->addrsize]; in verify_gla()
2902 printf("verify_gla mismatch: segbase(0x%0lx)" in verify_gla()
2903 "base(0x%0lx), scale(%d), index(0x%0lx), " in verify_gla()
2904 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n", in verify_gla()
2905 segbase, base, vie->scale, idx, vie->displacement, in verify_gla()
2907 return (-1); in verify_gla()
2910 return (0); in verify_gla()
2924 return (-1); in vmm_decode_instruction()
2927 return (-1); in vmm_decode_instruction()
2930 return (-1); in vmm_decode_instruction()
2933 return (-1); in vmm_decode_instruction()
2936 return (-1); in vmm_decode_instruction()
2939 return (-1); in vmm_decode_instruction()
2942 return (-1); in vmm_decode_instruction()
2945 if ((vie->op.op_flags & VIE_OP_F_NO_GLA_VERIFICATION) == 0) { in vmm_decode_instruction()
2947 return (-1); in vmm_decode_instruction()
2951 vie->decoded = 1; /* success */ in vmm_decode_instruction()
2953 return (0); in vmm_decode_instruction()