Lines Matching +full:gpa +full:- +full:0
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
70 VIE_OP_TYPE_NONE = 0,
93 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
94 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
95 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
100 [0xF7] = {
101 .op_byte = 0xF7,
107 [0xAE] = {
108 .op_byte = 0xAE,
111 [0xB6] = {
112 .op_byte = 0xB6,
115 [0xB7] = {
116 .op_byte = 0xB7,
119 [0xBA] = {
120 .op_byte = 0xBA,
124 [0xBE] = {
125 .op_byte = 0xBE,
131 [0x03] = {
132 .op_byte = 0x03,
135 [0x0F] = {
136 .op_byte = 0x0F,
139 [0x0B] = {
140 .op_byte = 0x0B,
143 [0x2B] = {
144 .op_byte = 0x2B,
147 [0x39] = {
148 .op_byte = 0x39,
151 [0x3B] = {
152 .op_byte = 0x3B,
155 [0x88] = {
156 .op_byte = 0x88,
159 [0x89] = {
160 .op_byte = 0x89,
163 [0x8A] = {
164 .op_byte = 0x8A,
167 [0x8B] = {
168 .op_byte = 0x8B,
171 [0xA1] = {
172 .op_byte = 0xA1,
176 [0xA3] = {
177 .op_byte = 0xA3,
181 [0xA4] = {
182 .op_byte = 0xA4,
186 [0xA5] = {
187 .op_byte = 0xA5,
191 [0xAA] = {
192 .op_byte = 0xAA,
196 [0xAB] = {
197 .op_byte = 0xAB,
201 [0xC6] = {
202 /* XXX Group 11 extended opcode - not just MOV */
203 .op_byte = 0xC6,
207 [0xC7] = {
208 .op_byte = 0xC7,
212 [0x23] = {
213 .op_byte = 0x23,
216 [0x80] = {
218 .op_byte = 0x80,
222 [0x81] = {
224 .op_byte = 0x81,
228 [0x83] = {
230 .op_byte = 0x83,
234 [0x8F] = {
235 /* XXX Group 1A extended opcode - not just POP */
236 .op_byte = 0x8F,
239 [0xF7] = {
240 /* XXX Group 3 extended opcode - not just TEST */
241 .op_byte = 0xF7,
245 [0xFF] = {
246 /* XXX Group 5 extended opcode - not just PUSH */
247 .op_byte = 0xFF,
253 #define VIE_MOD_INDIRECT 0
284 [1] = 0xff,
285 [2] = 0xffff,
286 [4] = 0xffffffff,
287 [8] = 0xffffffffffffffff,
303 *lhbr = 0; in vie_calc_bytereg()
304 *reg = gpr_map[vie->reg]; in vie_calc_bytereg()
307 * 64-bit mode imposes limitations on accessing legacy high byte in vie_calc_bytereg()
310 * The legacy high-byte registers cannot be addressed if the REX in vie_calc_bytereg()
315 * of the 'ModRM:reg' field address the legacy high-byte registers, in vie_calc_bytereg()
318 if (!vie->rex_present) { in vie_calc_bytereg()
319 if (vie->reg & 0x4) { in vie_calc_bytereg()
321 *reg = gpr_map[vie->reg & 0x3]; in vie_calc_bytereg()
356 if (error == 0) { in vie_write_bytereg()
358 mask = 0xff; in vie_write_bytereg()
390 val &= 0xffffffffUL; in vie_update_register()
405 * Return the status flags that would result from doing (x - y).
413 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
448 __asm __volatile("add %2,%1; pushfq; popq %0" : \
483 __asm __volatile("and %2,%1; pushfq; popq %0" : \
510 emulate_mov(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_mov() argument
518 size = vie->opsize; in emulate_mov()
521 switch (vie->op.op_byte) { in emulate_mov()
522 case 0x88: in emulate_mov()
530 if (error == 0) in emulate_mov()
531 error = memwrite(vcpu, gpa, byte, size, arg); in emulate_mov()
533 case 0x89: in emulate_mov()
540 reg = gpr_map[vie->reg]; in emulate_mov()
542 if (error == 0) { in emulate_mov()
544 error = memwrite(vcpu, gpa, val, size, arg); in emulate_mov()
547 case 0x8A: in emulate_mov()
554 error = memread(vcpu, gpa, &val, size, arg); in emulate_mov()
555 if (error == 0) in emulate_mov()
558 case 0x8B: in emulate_mov()
565 error = memread(vcpu, gpa, &val, size, arg); in emulate_mov()
566 if (error == 0) { in emulate_mov()
567 reg = gpr_map[vie->reg]; in emulate_mov()
571 case 0xA1: in emulate_mov()
578 error = memread(vcpu, gpa, &val, size, arg); in emulate_mov()
579 if (error == 0) { in emulate_mov()
584 case 0xA3: in emulate_mov()
592 if (error == 0) { in emulate_mov()
594 error = memwrite(vcpu, gpa, val, size, arg); in emulate_mov()
597 case 0xC6: in emulate_mov()
600 * C6/0 mov r/m8, imm8 in emulate_mov()
601 * REX + C6/0 mov r/m8, imm8 in emulate_mov()
604 error = memwrite(vcpu, gpa, vie->immediate, size, arg); in emulate_mov()
606 case 0xC7: in emulate_mov()
609 * C7/0 mov r/m16, imm16 in emulate_mov()
610 * C7/0 mov r/m32, imm32 in emulate_mov()
611 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits) in emulate_mov()
613 val = vie->immediate & size2mask[size]; in emulate_mov()
614 error = memwrite(vcpu, gpa, val, size, arg); in emulate_mov()
624 emulate_movx(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_movx() argument
631 size = vie->opsize; in emulate_movx()
634 switch (vie->op.op_byte) { in emulate_movx()
635 case 0xB6: in emulate_movx()
640 * 0F B6/r movzx r16, r/m8 in emulate_movx()
641 * 0F B6/r movzx r32, r/m8 in emulate_movx()
642 * REX.W + 0F B6/r movzx r64, r/m8 in emulate_movx()
646 error = memread(vcpu, gpa, &val, 1, arg); in emulate_movx()
651 reg = gpr_map[vie->reg]; in emulate_movx()
653 /* zero-extend byte */ in emulate_movx()
659 case 0xB7: in emulate_movx()
664 * 0F B7/r movzx r32, r/m16 in emulate_movx()
665 * REX.W + 0F B7/r movzx r64, r/m16 in emulate_movx()
667 error = memread(vcpu, gpa, &val, 2, arg); in emulate_movx()
671 reg = gpr_map[vie->reg]; in emulate_movx()
673 /* zero-extend word */ in emulate_movx()
678 case 0xBE: in emulate_movx()
683 * 0F BE/r movsx r16, r/m8 in emulate_movx()
684 * 0F BE/r movsx r32, r/m8 in emulate_movx()
685 * REX.W + 0F BE/r movsx r64, r/m8 in emulate_movx()
689 error = memread(vcpu, gpa, &val, 1, arg); in emulate_movx()
694 reg = gpr_map[vie->reg]; in emulate_movx()
721 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error)); in get_gla()
724 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in get_gla()
727 KASSERT(error == 0, ("%s: error %d getting segment descriptor %d", in get_gla()
731 KASSERT(error == 0, ("%s: error %d getting register %d", __func__, in get_gla()
734 if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize, in get_gla()
737 vm_inject_ss(vcpu, 0); in get_gla()
743 if (vie_canonical_check(paging->cpu_mode, *gla)) { in get_gla()
745 vm_inject_ss(vcpu, 0); in get_gla()
751 if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) { in get_gla()
752 vm_inject_ac(vcpu, 0); in get_gla()
756 *fault = 0; in get_gla()
757 return (0); in get_gla()
761 return (0); in get_gla()
765 emulate_movs(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_movs() argument
778 opsize = (vie->op.op_byte == 0xA4) ? 1 : vie->opsize; in emulate_movs()
779 val = 0; in emulate_movs()
780 error = 0; in emulate_movs()
789 repeat = vie->repz_present | vie->repnz_present; in emulate_movs()
799 if ((rcx & vie_size2mask(vie->addrsize)) == 0) { in emulate_movs()
800 error = 0; in emulate_movs()
807 * -------------------------------------------- in emulate_movs()
817 * XXX the emulation doesn't properly handle the case where 'gpa' in emulate_movs()
821 seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS; in emulate_movs()
822 error = get_gla(vcpu, vie, paging, opsize, vie->addrsize, in emulate_movs()
829 if (error == 0) { in emulate_movs()
838 error = memwrite(vcpu, gpa, val, opsize, arg); in emulate_movs()
847 error = get_gla(vcpu, vie, paging, opsize, vie->addrsize, in emulate_movs()
855 if (error == 0) { in emulate_movs()
862 * A MMIO read can have side-effects so we in emulate_movs()
864 * successful. If a page-fault needs to be in emulate_movs()
868 error = memread(vcpu, gpa, &val, opsize, arg); in emulate_movs()
879 * side-effects) only after we are sure that the in emulate_movs()
904 KASSERT(error == 0, ("%s: error %d getting rsi", __func__, error)); in emulate_movs()
907 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error)); in emulate_movs()
910 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_movs()
913 rsi -= opsize; in emulate_movs()
914 rdi -= opsize; in emulate_movs()
921 vie->addrsize); in emulate_movs()
922 KASSERT(error == 0, ("%s: error %d updating rsi", __func__, error)); in emulate_movs()
925 vie->addrsize); in emulate_movs()
926 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error)); in emulate_movs()
929 rcx = rcx - 1; in emulate_movs()
931 rcx, vie->addrsize); in emulate_movs()
937 if ((rcx & vie_size2mask(vie->addrsize)) != 0) in emulate_movs()
941 KASSERT(error == 0 || error == EFAULT, ("%s: unexpected error %d", in emulate_movs()
947 emulate_stos(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_stos() argument
955 opsize = (vie->op.op_byte == 0xAA) ? 1 : vie->opsize; in emulate_stos()
956 repeat = vie->repz_present | vie->repnz_present; in emulate_stos()
966 if ((rcx & vie_size2mask(vie->addrsize)) == 0) in emulate_stos()
967 return (0); in emulate_stos()
973 error = memwrite(vcpu, gpa, val, opsize, arg); in emulate_stos()
978 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error)); in emulate_stos()
981 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_stos()
984 rdi -= opsize; in emulate_stos()
989 vie->addrsize); in emulate_stos()
990 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error)); in emulate_stos()
993 rcx = rcx - 1; in emulate_stos()
995 rcx, vie->addrsize); in emulate_stos()
1001 if ((rcx & vie_size2mask(vie->addrsize)) != 0) in emulate_stos()
1005 return (0); in emulate_stos()
1009 emulate_and(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_and() argument
1016 size = vie->opsize; in emulate_and()
1019 switch (vie->op.op_byte) { in emulate_and()
1020 case 0x23: in emulate_and()
1031 reg = gpr_map[vie->reg]; in emulate_and()
1037 error = memread(vcpu, gpa, &val2, size, arg); in emulate_and()
1045 case 0x81: in emulate_and()
1046 case 0x83: in emulate_and()
1053 * REX.W + 81 /4 and r/m64, imm32 sign-extended to 64 in emulate_and()
1055 * 83 /4 and r/m16, imm8 sign-extended to 16 in emulate_and()
1056 * 83 /4 and r/m32, imm8 sign-extended to 32 in emulate_and()
1057 * REX.W + 83/4 and r/m64, imm8 sign-extended to 64 in emulate_and()
1061 error = memread(vcpu, gpa, &val1, size, arg); in emulate_and()
1066 * perform the operation with the pre-fetched immediate in emulate_and()
1069 result = val1 & vie->immediate; in emulate_and()
1070 error = memwrite(vcpu, gpa, result, size, arg); in emulate_and()
1086 * The updated status flags are obtained by subtracting 0 from 'result'. in emulate_and()
1088 rflags2 = getcc(size, result, 0); in emulate_and()
1097 emulate_or(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_or() argument
1104 size = vie->opsize; in emulate_or()
1107 switch (vie->op.op_byte) { in emulate_or()
1108 case 0x0B: in emulate_or()
1113 * 0b/r or r16, r/m16 in emulate_or()
1114 * 0b/r or r32, r/m32 in emulate_or()
1115 * REX.W + 0b/r or r64, r/m64 in emulate_or()
1119 reg = gpr_map[vie->reg]; in emulate_or()
1125 error = memread(vcpu, gpa, &val2, size, arg); in emulate_or()
1133 case 0x81: in emulate_or()
1134 case 0x83: in emulate_or()
1141 * REX.W + 81 /1 or r/m64, imm32 sign-extended to 64 in emulate_or()
1143 * 83 /1 or r/m16, imm8 sign-extended to 16 in emulate_or()
1144 * 83 /1 or r/m32, imm8 sign-extended to 32 in emulate_or()
1145 * REX.W + 83/1 or r/m64, imm8 sign-extended to 64 in emulate_or()
1149 error = memread(vcpu, gpa, &val1, size, arg); in emulate_or()
1154 * perform the operation with the pre-fetched immediate in emulate_or()
1157 result = val1 | vie->immediate; in emulate_or()
1158 error = memwrite(vcpu, gpa, result, size, arg); in emulate_or()
1174 * The updated status flags are obtained by subtracting 0 from 'result'. in emulate_or()
1176 rflags2 = getcc(size, result, 0); in emulate_or()
1185 emulate_cmp(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_cmp() argument
1192 size = vie->opsize; in emulate_cmp()
1193 switch (vie->op.op_byte) { in emulate_cmp()
1194 case 0x39: in emulate_cmp()
1195 case 0x3B: in emulate_cmp()
1212 reg = gpr_map[vie->reg]; in emulate_cmp()
1218 error = memread(vcpu, gpa, &memop, size, arg); in emulate_cmp()
1222 if (vie->op.op_byte == 0x3B) { in emulate_cmp()
1231 case 0x80: in emulate_cmp()
1232 case 0x81: in emulate_cmp()
1233 case 0x83: in emulate_cmp()
1240 * REX.W + 81 /7 cmp r/m64, imm32 sign-extended to 64 in emulate_cmp()
1242 * 83 /7 cmp r/m16, imm8 sign-extended to 16 in emulate_cmp()
1243 * 83 /7 cmp r/m32, imm8 sign-extended to 32 in emulate_cmp()
1244 * REX.W + 83 /7 cmp r/m64, imm8 sign-extended to 64 in emulate_cmp()
1253 if (vie->op.op_byte == 0x80) in emulate_cmp()
1257 error = memread(vcpu, gpa, &op1, size, arg); in emulate_cmp()
1261 rflags2 = getcc(size, op1, vie->immediate); in emulate_cmp()
1277 emulate_test(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_test() argument
1283 size = vie->opsize; in emulate_test()
1286 switch (vie->op.op_byte) { in emulate_test()
1287 case 0xF7: in emulate_test()
1289 * F7 /0 test r/m16, imm16 in emulate_test()
1290 * F7 /0 test r/m32, imm32 in emulate_test()
1291 * REX.W + F7 /0 test r/m64, imm32 sign-extended to 64 in emulate_test()
1298 if ((vie->reg & 7) != 0) in emulate_test()
1301 error = memread(vcpu, gpa, &op1, size, arg); in emulate_test()
1305 rflags2 = getandflags(size, op1, vie->immediate); in emulate_test()
1326 emulate_bextr(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_bextr() argument
1334 size = vie->opsize; in emulate_bextr()
1338 * VEX.LZ.0F38.W0 F7 /r BEXTR r32a, r/m32, r32b in emulate_bextr()
1339 * VEX.LZ.0F38.W1 F7 /r BEXTR r64a, r/m64, r64b in emulate_bextr()
1344 * Operand size is always 32-bit if not in 64-bit mode (W1 is ignored). in emulate_bextr()
1346 if (size != 4 && paging->cpu_mode != CPU_MODE_64BIT) in emulate_bextr()
1354 error = memread(vcpu, gpa, &src1, size, arg); in emulate_bextr()
1357 error = vie_read_register(vcpu, gpr_map[vie->vex_reg], &src2); in emulate_bextr()
1364 start = (src2 & 0xff); in emulate_bextr()
1365 len = (src2 & 0xff00) >> 8; in emulate_bextr()
1368 dst = 0; in emulate_bextr()
1375 len = (size * 8) - start; in emulate_bextr()
1376 if (len == 0) in emulate_bextr()
1379 if (start > 0) in emulate_bextr()
1382 src1 = src1 & ((1ull << len) - 1); in emulate_bextr()
1386 error = vie_update_register(vcpu, gpr_map[vie->reg], dst, size); in emulate_bextr()
1395 if (dst == 0) in emulate_bextr()
1403 emulate_add(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_add() argument
1410 size = vie->opsize; in emulate_add()
1413 switch (vie->op.op_byte) { in emulate_add()
1414 case 0x03: in emulate_add()
1424 reg = gpr_map[vie->reg]; in emulate_add()
1430 error = memread(vcpu, gpa, &val2, size, arg); in emulate_add()
1459 emulate_sub(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_sub() argument
1466 size = vie->opsize; in emulate_sub()
1469 switch (vie->op.op_byte) { in emulate_sub()
1470 case 0x2B: in emulate_sub()
1480 reg = gpr_map[vie->reg]; in emulate_sub()
1486 error = memread(vcpu, gpa, &val2, size, arg); in emulate_sub()
1491 nval = val1 - val2; in emulate_sub()
1528 val = 0; in emulate_stack_op()
1529 size = vie->opsize; in emulate_stack_op()
1530 pushop = (vie->op.op_type == VIE_OP_TYPE_PUSH) ? 1 : 0; in emulate_stack_op()
1533 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1 in emulate_stack_op()
1535 if (paging->cpu_mode == CPU_MODE_REAL) { in emulate_stack_op()
1537 } else if (paging->cpu_mode == CPU_MODE_64BIT) { in emulate_stack_op()
1539 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3 in emulate_stack_op()
1540 * - Stack pointer size is always 64-bits. in emulate_stack_op()
1541 * - PUSH/POP of 32-bit values is not possible in 64-bit mode. in emulate_stack_op()
1542 * - 16-bit PUSH/POP is supported by using the operand size in emulate_stack_op()
1546 size = vie->opsize_override ? 2 : 8; in emulate_stack_op()
1550 * stack-segment descriptor determines the size of the in emulate_stack_op()
1554 KASSERT(error == 0, ("%s: error %d getting SS descriptor", in emulate_stack_op()
1563 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error)); in emulate_stack_op()
1566 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_stack_op()
1569 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error)); in emulate_stack_op()
1571 rsp -= size; in emulate_stack_op()
1574 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc, in emulate_stack_op()
1577 vm_inject_ss(vcpu, 0); in emulate_stack_op()
1578 return (0); in emulate_stack_op()
1581 if (vie_canonical_check(paging->cpu_mode, stack_gla)) { in emulate_stack_op()
1582 vm_inject_ss(vcpu, 0); in emulate_stack_op()
1583 return (0); in emulate_stack_op()
1586 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) { in emulate_stack_op()
1587 vm_inject_ac(vcpu, 0); in emulate_stack_op()
1588 return (0); in emulate_stack_op()
1599 if (error == 0) in emulate_stack_op()
1608 if (error == 0) { in emulate_stack_op()
1611 KASSERT(error == 0, ("error %d updating rsp", error)); in emulate_stack_op()
1624 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2. in emulate_push()
1629 if ((vie->reg & 7) != 6) in emulate_push()
1645 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2. in emulate_pop()
1650 if ((vie->reg & 7) != 0) in emulate_pop()
1659 emulate_group1(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_group1() argument
1665 switch (vie->reg & 7) { in emulate_group1()
1666 case 0x1: /* OR */ in emulate_group1()
1667 error = emulate_or(vcpu, gpa, vie, in emulate_group1()
1670 case 0x4: /* AND */ in emulate_group1()
1671 error = emulate_and(vcpu, gpa, vie, in emulate_group1()
1674 case 0x7: /* CMP */ in emulate_group1()
1675 error = emulate_cmp(vcpu, gpa, vie, in emulate_group1()
1687 emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_bittest() argument
1695 * 0F BA is a Group 8 extended opcode. in emulate_bittest()
1700 if ((vie->reg & 7) != 4) in emulate_bittest()
1704 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error)); in emulate_bittest()
1706 error = memread(vcpu, gpa, &val, vie->opsize, memarg); in emulate_bittest()
1711 * Intel SDM, Vol 2, Table 3-2: in emulate_bittest()
1714 bitmask = vie->opsize * 8 - 1; in emulate_bittest()
1715 bitoff = vie->immediate & bitmask; in emulate_bittest()
1724 KASSERT(error == 0, ("%s: error %d updating rflags", __func__, error)); in emulate_bittest()
1726 return (0); in emulate_bittest()
1730 emulate_twob_group15(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in emulate_twob_group15() argument
1737 switch (vie->reg & 7) { in emulate_twob_group15()
1738 case 0x7: /* CLFLUSH, CLFLUSHOPT, and SFENCE */ in emulate_twob_group15()
1739 if (vie->mod == 0x3) { in emulate_twob_group15()
1744 error = 0; in emulate_twob_group15()
1750 error = memread(vcpu, gpa, &buf, 1, memarg); in emulate_twob_group15()
1762 vmm_emulate_instruction(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, in vmm_emulate_instruction() argument
1768 if (!vie->decoded) in vmm_emulate_instruction()
1771 switch (vie->op.op_type) { in vmm_emulate_instruction()
1773 error = emulate_group1(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1777 error = emulate_pop(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1781 error = emulate_push(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1785 error = emulate_cmp(vcpu, gpa, vie, in vmm_emulate_instruction()
1789 error = emulate_mov(vcpu, gpa, vie, in vmm_emulate_instruction()
1794 error = emulate_movx(vcpu, gpa, vie, in vmm_emulate_instruction()
1798 error = emulate_movs(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1802 error = emulate_stos(vcpu, gpa, vie, paging, memread, in vmm_emulate_instruction()
1806 error = emulate_and(vcpu, gpa, vie, in vmm_emulate_instruction()
1810 error = emulate_or(vcpu, gpa, vie, in vmm_emulate_instruction()
1814 error = emulate_sub(vcpu, gpa, vie, in vmm_emulate_instruction()
1818 error = emulate_bittest(vcpu, gpa, vie, in vmm_emulate_instruction()
1822 error = emulate_twob_group15(vcpu, gpa, vie, in vmm_emulate_instruction()
1826 error = emulate_add(vcpu, gpa, vie, memread, in vmm_emulate_instruction()
1830 error = emulate_test(vcpu, gpa, vie, in vmm_emulate_instruction()
1834 error = emulate_bextr(vcpu, gpa, vie, paging, in vmm_emulate_instruction()
1850 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl)); in vie_alignment_check()
1852 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0) in vie_alignment_check()
1853 return (0); in vie_alignment_check()
1855 return ((gla & (size - 1)) ? 1 : 0); in vie_alignment_check()
1864 return (0); in vie_canonical_check()
1870 mask = ~((1UL << 48) - 1); in vie_canonical_check()
1874 return ((gla & mask) != 0); in vie_canonical_check()
1897 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0, in vie_calculate_gla()
1912 * it results in a #GP(0). in vie_calculate_gla()
1914 if (SEG_DESC_UNUSABLE(desc->access)) in vie_calculate_gla()
1915 return (-1); in vie_calculate_gla()
1921 * it would have been checked before the VM-exit. in vie_calculate_gla()
1923 KASSERT(SEG_DESC_PRESENT(desc->access), in vie_calculate_gla()
1924 ("segment %d not present: %#x", seg, desc->access)); in vie_calculate_gla()
1929 type = SEG_DESC_TYPE(desc->access); in vie_calculate_gla()
1934 /* #GP on a read access to a exec-only code segment */ in vie_calculate_gla()
1935 if ((type & 0xA) == 0x8) in vie_calculate_gla()
1936 return (-1); in vie_calculate_gla()
1942 * read-only data segment. in vie_calculate_gla()
1944 if (type & 0x8) /* code segment */ in vie_calculate_gla()
1945 return (-1); in vie_calculate_gla()
1947 if ((type & 0xA) == 0) /* read-only data seg */ in vie_calculate_gla()
1948 return (-1); in vie_calculate_gla()
1952 * 'desc->limit' is fully expanded taking granularity into in vie_calculate_gla()
1955 if ((type & 0xC) == 0x4) { in vie_calculate_gla()
1956 /* expand-down data segment */ in vie_calculate_gla()
1957 low_limit = desc->limit + 1; in vie_calculate_gla()
1958 high_limit = SEG_DESC_DEF32(desc->access) ? in vie_calculate_gla()
1959 0xffffffff : 0xffff; in vie_calculate_gla()
1961 /* code segment or expand-up data segment */ in vie_calculate_gla()
1962 low_limit = 0; in vie_calculate_gla()
1963 high_limit = desc->limit; in vie_calculate_gla()
1966 while (length > 0) { in vie_calculate_gla()
1969 return (-1); in vie_calculate_gla()
1971 length--; in vie_calculate_gla()
1976 * In 64-bit mode all segments except %fs and %gs have a segment in vie_calculate_gla()
1977 * base address of 0. in vie_calculate_gla()
1981 segbase = 0; in vie_calculate_gla()
1983 segbase = desc->base; in vie_calculate_gla()
1992 return (0); in vie_calculate_gla()
2006 memset((char *)vie + offsetof(struct vie, vie_startzero), 0, in vie_restart()
2007 sizeof(*vie) - offsetof(struct vie, vie_startzero)); in vie_restart()
2009 vie->base_register = VM_REG_LAST; in vie_restart()
2010 vie->index_register = VM_REG_LAST; in vie_restart()
2011 vie->segment_register = VM_REG_LAST; in vie_restart()
2017 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE, in vie_init()
2021 memset(vie->inst, 0, sizeof(vie->inst)); in vie_init()
2022 if (inst_length != 0) in vie_init()
2023 memcpy(vie->inst, inst_bytes, inst_length); in vie_init()
2024 vie->num_valid = inst_length; in vie_init()
2031 int error_code = 0; in pf_error_code()
2068 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault, bool check_only) in _vm_gla2gpa() argument
2076 *guest_fault = 0; in _vm_gla2gpa()
2078 usermode = (paging->cpl == 3 ? 1 : 0); in _vm_gla2gpa()
2081 retval = 0; in _vm_gla2gpa()
2082 retries = 0; in _vm_gla2gpa()
2084 ptpphys = paging->cr3; /* root of the page tables */ in _vm_gla2gpa()
2086 if (retries++ > 0) in _vm_gla2gpa()
2089 if (vie_canonical_check(paging->cpu_mode, gla)) { in _vm_gla2gpa()
2091 * XXX assuming a non-stack reference otherwise a stack fault in _vm_gla2gpa()
2099 if (paging->paging_mode == PAGING_MODE_FLAT) { in _vm_gla2gpa()
2100 *gpa = gla; in _vm_gla2gpa()
2104 if (paging->paging_mode == PAGING_MODE_32) { in _vm_gla2gpa()
2106 while (--nlevels >= 0) { in _vm_gla2gpa()
2108 ptpphys &= ~0xfff; in _vm_gla2gpa()
2117 ptpindex = (gla >> ptpshift) & 0x3FF; in _vm_gla2gpa()
2122 if ((pte32 & PG_V) == 0 || in _vm_gla2gpa()
2123 (usermode && (pte32 & PG_U) == 0) || in _vm_gla2gpa()
2124 (writable && (pte32 & PG_RW) == 0)) { in _vm_gla2gpa()
2126 pfcode = pf_error_code(usermode, prot, 0, in _vm_gla2gpa()
2140 if (!check_only && (pte32 & PG_A) == 0) { in _vm_gla2gpa()
2142 pte32, pte32 | PG_A) == 0) { in _vm_gla2gpa()
2147 /* XXX must be ignored if CR4.PSE=0 */ in _vm_gla2gpa()
2148 if (nlevels > 0 && (pte32 & PG_PS) != 0) in _vm_gla2gpa()
2155 if (!check_only && writable && (pte32 & PG_M) == 0) { in _vm_gla2gpa()
2157 pte32, pte32 | PG_M) == 0) { in _vm_gla2gpa()
2164 *gpa = pte32 | (gla & (pgsize - 1)); in _vm_gla2gpa()
2168 if (paging->paging_mode == PAGING_MODE_PAE) { in _vm_gla2gpa()
2170 ptpphys &= 0xffffffe0UL; in _vm_gla2gpa()
2177 ptpindex = (gla >> 30) & 0x3; in _vm_gla2gpa()
2181 if ((pte & PG_V) == 0) { in _vm_gla2gpa()
2183 pfcode = pf_error_code(usermode, prot, 0, pte); in _vm_gla2gpa()
2192 } else if (paging->paging_mode == PAGING_MODE_64_LA57) { in _vm_gla2gpa()
2198 while (--nlevels >= 0) { in _vm_gla2gpa()
2207 ptpindex = (gla >> ptpshift) & 0x1FF; in _vm_gla2gpa()
2212 if ((pte & PG_V) == 0 || in _vm_gla2gpa()
2213 (usermode && (pte & PG_U) == 0) || in _vm_gla2gpa()
2214 (writable && (pte & PG_RW) == 0)) { in _vm_gla2gpa()
2216 pfcode = pf_error_code(usermode, prot, 0, pte); in _vm_gla2gpa()
2223 if (!check_only && (pte & PG_A) == 0) { in _vm_gla2gpa()
2225 pte, pte | PG_A) == 0) { in _vm_gla2gpa()
2230 if (nlevels > 0 && (pte & PG_PS) != 0) { in _vm_gla2gpa()
2246 if (!check_only && writable && (pte & PG_M) == 0) { in _vm_gla2gpa()
2247 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0) in _vm_gla2gpa()
2253 *gpa = pte | (gla & (pgsize - 1)); in _vm_gla2gpa()
2256 KASSERT(retval == 0 || retval == EFAULT, ("%s: unexpected retval %d", in _vm_gla2gpa()
2269 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault) in vm_gla2gpa() argument
2272 return (_vm_gla2gpa(vcpu, paging, gla, prot, gpa, guest_fault, in vm_gla2gpa()
2278 uint64_t gla, int prot, uint64_t *gpa, int *guest_fault) in vm_gla2gpa_nofault() argument
2281 return (_vm_gla2gpa(vcpu, paging, gla, prot, gpa, guest_fault, in vm_gla2gpa_nofault()
2301 vm_copyin(copyinfo, vie->inst, inst_length); in vmm_fetch_instruction()
2303 vie->num_valid = inst_length; in vmm_fetch_instruction()
2304 return (0); in vmm_fetch_instruction()
2312 if (vie->num_processed < vie->num_valid) { in vie_peek()
2313 *x = vie->inst[vie->num_processed]; in vie_peek()
2314 return (0); in vie_peek()
2316 return (-1); in vie_peek()
2323 vie->num_processed++; in vie_advance()
2331 case 0x2E: in segment_override()
2334 case 0x36: in segment_override()
2337 case 0x3E: in segment_override()
2340 case 0x26: in segment_override()
2343 case 0x64: in segment_override()
2346 case 0x65: in segment_override()
2362 return (-1); in decode_prefixes()
2364 if (x == 0x66) in decode_prefixes()
2365 vie->opsize_override = 1; in decode_prefixes()
2366 else if (x == 0x67) in decode_prefixes()
2367 vie->addrsize_override = 1; in decode_prefixes()
2368 else if (x == 0xF3) in decode_prefixes()
2369 vie->repz_present = 1; in decode_prefixes()
2370 else if (x == 0xF2) in decode_prefixes()
2371 vie->repnz_present = 1; in decode_prefixes()
2372 else if (segment_override(x, &vie->segment_register)) in decode_prefixes()
2373 vie->segment_override = 1; in decode_prefixes()
2382 * - Only one REX prefix is allowed per instruction. in decode_prefixes()
2383 * - The REX prefix must immediately precede the opcode byte or the in decode_prefixes()
2385 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3) in decode_prefixes()
2388 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) { in decode_prefixes()
2389 vie->rex_present = 1; in decode_prefixes()
2390 vie->rex_w = x & 0x8 ? 1 : 0; in decode_prefixes()
2391 vie->rex_r = x & 0x4 ? 1 : 0; in decode_prefixes()
2392 vie->rex_x = x & 0x2 ? 1 : 0; in decode_prefixes()
2393 vie->rex_b = x & 0x1 ? 1 : 0; in decode_prefixes()
2401 && x == 0xC4) { in decode_prefixes()
2404 /* 3-byte VEX prefix. */ in decode_prefixes()
2405 vie->vex_present = 1; in decode_prefixes()
2409 return (-1); in decode_prefixes()
2412 * 2nd byte: [R', X', B', mmmmm[4:0]]. Bits are inverted in decode_prefixes()
2415 vie->rex_r = x & 0x80 ? 0 : 1; in decode_prefixes()
2416 vie->rex_x = x & 0x40 ? 0 : 1; in decode_prefixes()
2417 vie->rex_b = x & 0x20 ? 0 : 1; in decode_prefixes()
2419 switch (x & 0x1F) { in decode_prefixes()
2420 case 0x2: in decode_prefixes()
2421 /* 0F 38. */ in decode_prefixes()
2424 case 0x1: in decode_prefixes()
2425 /* 0F class - nothing handled here yet. */ in decode_prefixes()
2427 case 0x3: in decode_prefixes()
2428 /* 0F 3A class - nothing handled here yet. */ in decode_prefixes()
2432 return (-1); in decode_prefixes()
2437 return (-1); in decode_prefixes()
2439 /* 3rd byte: [W, vvvv[6:3], L, pp[1:0]]. */ in decode_prefixes()
2440 vie->rex_w = x & 0x80 ? 1 : 0; in decode_prefixes()
2442 vie->vex_reg = ((~(unsigned)x & 0x78u) >> 3); in decode_prefixes()
2443 vie->vex_l = !!(x & 0x4); in decode_prefixes()
2444 vie->vex_pp = (x & 0x3); in decode_prefixes()
2447 switch (vie->vex_pp) { in decode_prefixes()
2448 case 0x1: in decode_prefixes()
2449 vie->opsize_override = 1; in decode_prefixes()
2451 case 0x2: in decode_prefixes()
2452 vie->repz_present = 1; in decode_prefixes()
2454 case 0x3: in decode_prefixes()
2455 vie->repnz_present = 1; in decode_prefixes()
2463 return (-1); in decode_prefixes()
2465 vie->op = optab[x]; in decode_prefixes()
2466 if (vie->op.op_type == VIE_OP_TYPE_NONE) in decode_prefixes()
2467 return (-1); in decode_prefixes()
2473 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1 in decode_prefixes()
2477 * Default address size is 64-bits and default operand size in decode_prefixes()
2478 * is 32-bits. in decode_prefixes()
2480 vie->addrsize = vie->addrsize_override ? 4 : 8; in decode_prefixes()
2481 if (vie->rex_w) in decode_prefixes()
2482 vie->opsize = 8; in decode_prefixes()
2483 else if (vie->opsize_override) in decode_prefixes()
2484 vie->opsize = 2; in decode_prefixes()
2486 vie->opsize = 4; in decode_prefixes()
2488 /* Default address and operand sizes are 32-bits */ in decode_prefixes()
2489 vie->addrsize = vie->addrsize_override ? 2 : 4; in decode_prefixes()
2490 vie->opsize = vie->opsize_override ? 2 : 4; in decode_prefixes()
2492 /* Default address and operand sizes are 16-bits */ in decode_prefixes()
2493 vie->addrsize = vie->addrsize_override ? 4 : 2; in decode_prefixes()
2494 vie->opsize = vie->opsize_override ? 4 : 2; in decode_prefixes()
2496 return (0); in decode_prefixes()
2505 return (-1); in decode_two_byte_opcode()
2507 vie->op = two_byte_opcodes[x]; in decode_two_byte_opcode()
2509 if (vie->op.op_type == VIE_OP_TYPE_NONE) in decode_two_byte_opcode()
2510 return (-1); in decode_two_byte_opcode()
2513 return (0); in decode_two_byte_opcode()
2522 return (-1); in decode_opcode()
2525 if (vie->op.op_type != VIE_OP_TYPE_NONE) in decode_opcode()
2526 return (0); in decode_opcode()
2528 vie->op = one_byte_opcodes[x]; in decode_opcode()
2530 if (vie->op.op_type == VIE_OP_TYPE_NONE) in decode_opcode()
2531 return (-1); in decode_opcode()
2535 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE) in decode_opcode()
2538 return (0); in decode_opcode()
2546 if (vie->op.op_flags & VIE_OP_F_NO_MODRM) in decode_modrm()
2547 return (0); in decode_modrm()
2550 return (-1); in decode_modrm()
2553 return (-1); in decode_modrm()
2555 vie->mod = (x >> 6) & 0x3; in decode_modrm()
2556 vie->rm = (x >> 0) & 0x7; in decode_modrm()
2557 vie->reg = (x >> 3) & 0x7; in decode_modrm()
2564 if (vie->mod == VIE_MOD_DIRECT) in decode_modrm()
2565 return (-1); in decode_modrm()
2567 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) || in decode_modrm()
2568 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) { in decode_modrm()
2570 * Table 2-5: Special Cases of REX Encodings in decode_modrm()
2572 * mod=0, r/m=5 is used in the compatibility mode to in decode_modrm()
2582 vie->rm |= (vie->rex_b << 3); in decode_modrm()
2585 vie->reg |= (vie->rex_r << 3); in decode_modrm()
2588 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB) in decode_modrm()
2591 vie->base_register = gpr_map[vie->rm]; in decode_modrm()
2593 switch (vie->mod) { in decode_modrm()
2595 vie->disp_bytes = 1; in decode_modrm()
2598 vie->disp_bytes = 4; in decode_modrm()
2601 if (vie->rm == VIE_RM_DISP32) { in decode_modrm()
2602 vie->disp_bytes = 4; in decode_modrm()
2604 * Table 2-7. RIP-Relative Addressing in decode_modrm()
2606 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32 in decode_modrm()
2611 vie->base_register = VM_REG_GUEST_RIP; in decode_modrm()
2613 vie->base_register = VM_REG_LAST; in decode_modrm()
2621 return (0); in decode_modrm()
2630 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB) in decode_sib()
2631 return (0); in decode_sib()
2634 return (-1); in decode_sib()
2636 /* De-construct the SIB byte */ in decode_sib()
2637 vie->ss = (x >> 6) & 0x3; in decode_sib()
2638 vie->index = (x >> 3) & 0x7; in decode_sib()
2639 vie->base = (x >> 0) & 0x7; in decode_sib()
2642 vie->index |= vie->rex_x << 3; in decode_sib()
2643 vie->base |= vie->rex_b << 3; in decode_sib()
2645 switch (vie->mod) { in decode_sib()
2647 vie->disp_bytes = 1; in decode_sib()
2650 vie->disp_bytes = 4; in decode_sib()
2654 if (vie->mod == VIE_MOD_INDIRECT && in decode_sib()
2655 (vie->base == 5 || vie->base == 13)) { in decode_sib()
2657 * Special case when base register is unused if mod = 0 in decode_sib()
2661 * Table 2-3: 32-bit Addressing Forms with the SIB Byte in decode_sib()
2662 * Table 2-5: Special Cases of REX Encodings in decode_sib()
2664 vie->disp_bytes = 4; in decode_sib()
2666 vie->base_register = gpr_map[vie->base]; in decode_sib()
2673 * Table 2-3: 32-bit Addressing Forms with the SIB Byte in decode_sib()
2674 * Table 2-5: Special Cases of REX Encodings in decode_sib()
2676 if (vie->index != 4) in decode_sib()
2677 vie->index_register = gpr_map[vie->index]; in decode_sib()
2680 if (vie->index_register < VM_REG_LAST) in decode_sib()
2681 vie->scale = 1 << vie->ss; in decode_sib()
2685 return (0); in decode_sib()
2700 if ((n = vie->disp_bytes) == 0) in decode_displacement()
2701 return (0); in decode_displacement()
2706 for (i = 0; i < n; i++) { in decode_displacement()
2708 return (-1); in decode_displacement()
2715 vie->displacement = u.signed8; /* sign-extended */ in decode_displacement()
2717 vie->displacement = u.signed32; /* sign-extended */ in decode_displacement()
2719 return (0); in decode_displacement()
2735 if (vie->op.op_flags & VIE_OP_F_IMM) { in decode_immediate()
2738 * In 64-bit mode the typical size of immediate operands in decode_immediate()
2739 * remains 32-bits. When the operand size if 64-bits, the in decode_immediate()
2740 * processor sign-extends all immediates to 64-bits prior in decode_immediate()
2743 if (vie->opsize == 4 || vie->opsize == 8) in decode_immediate()
2744 vie->imm_bytes = 4; in decode_immediate()
2746 vie->imm_bytes = 2; in decode_immediate()
2747 } else if (vie->op.op_flags & VIE_OP_F_IMM8) { in decode_immediate()
2748 vie->imm_bytes = 1; in decode_immediate()
2751 if ((n = vie->imm_bytes) == 0) in decode_immediate()
2752 return (0); in decode_immediate()
2757 for (i = 0; i < n; i++) { in decode_immediate()
2759 return (-1); in decode_immediate()
2765 /* sign-extend the immediate value before use */ in decode_immediate()
2767 vie->immediate = u.signed8; in decode_immediate()
2769 vie->immediate = u.signed16; in decode_immediate()
2771 vie->immediate = u.signed32; in decode_immediate()
2773 return (0); in decode_immediate()
2786 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0) in decode_moffset()
2787 return (0); in decode_moffset()
2790 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM: in decode_moffset()
2791 * The memory offset size follows the address-size of the instruction. in decode_moffset()
2793 n = vie->addrsize; in decode_moffset()
2796 u.u64 = 0; in decode_moffset()
2797 for (i = 0; i < n; i++) { in decode_moffset()
2799 return (-1); in decode_moffset()
2804 vie->displacement = u.u64; in decode_moffset()
2805 return (0); in decode_moffset()
2824 return (0); in verify_gla()
2826 base = 0; in verify_gla()
2827 if (vie->base_register != VM_REG_LAST) { in verify_gla()
2828 error = vm_get_register(vcpu, vie->base_register, &base); in verify_gla()
2831 error, vie->base_register); in verify_gla()
2832 return (-1); in verify_gla()
2836 * RIP-relative addressing starts from the following in verify_gla()
2839 if (vie->base_register == VM_REG_GUEST_RIP) in verify_gla()
2840 base += vie->num_processed; in verify_gla()
2843 idx = 0; in verify_gla()
2844 if (vie->index_register != VM_REG_LAST) { in verify_gla()
2845 error = vm_get_register(vcpu, vie->index_register, &idx); in verify_gla()
2848 error, vie->index_register); in verify_gla()
2849 return (-1); in verify_gla()
2856 * In 64-bit mode, segmentation is generally (but not in verify_gla()
2860 * In legacy IA-32 mode, when the ESP or EBP register is used in verify_gla()
2866 if (vie->segment_override) in verify_gla()
2867 seg = vie->segment_register; in verify_gla()
2868 else if (vie->base_register == VM_REG_GUEST_RSP || in verify_gla()
2869 vie->base_register == VM_REG_GUEST_RBP) in verify_gla()
2875 segbase = 0; in verify_gla()
2881 vie->segment_register); in verify_gla()
2882 return (-1); in verify_gla()
2887 gla2 = segbase + base + vie->scale * idx + vie->displacement; in verify_gla()
2888 gla2 &= size2mask[vie->addrsize]; in verify_gla()
2890 printf("verify_gla mismatch: segbase(0x%0lx)" in verify_gla()
2891 "base(0x%0lx), scale(%d), index(0x%0lx), " in verify_gla()
2892 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n", in verify_gla()
2893 segbase, base, vie->scale, idx, vie->displacement, in verify_gla()
2895 return (-1); in verify_gla()
2898 return (0); in verify_gla()
2912 return (-1); in vmm_decode_instruction()
2915 return (-1); in vmm_decode_instruction()
2918 return (-1); in vmm_decode_instruction()
2921 return (-1); in vmm_decode_instruction()
2924 return (-1); in vmm_decode_instruction()
2927 return (-1); in vmm_decode_instruction()
2930 return (-1); in vmm_decode_instruction()
2933 if ((vie->op.op_flags & VIE_OP_F_NO_GLA_VERIFICATION) == 0) { in vmm_decode_instruction()
2935 return (-1); in vmm_decode_instruction()
2939 vie->decoded = 1; /* success */ in vmm_decode_instruction()
2941 return (0); in vmm_decode_instruction()