1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
64 		int	 acnt;	/* sum of pin asserts (+1) and deasserts (-1) */
68 #define	VIOAPIC_LOCK(vioapic)		mtx_lock_spin(&((vioapic)->mtx))
69 #define	VIOAPIC_UNLOCK(vioapic)		mtx_unlock_spin(&((vioapic)->mtx))
70 #define	VIOAPIC_LOCKED(vioapic)		mtx_owned(&((vioapic)->mtx))
75 	VM_CTR1((vioapic)->vm, fmt, a1)
78 	VM_CTR2((vioapic)->vm, fmt, a1, a2)
81 	VM_CTR3((vioapic)->vm, fmt, a1, a2, a3)
84 	VM_CTR4((vioapic)->vm, fmt, a1, a2, a3, a4)
102 	uint32_t low, high, dest;  in vioapic_send_intr()  local
103 	bool level, phys;  in vioapic_send_intr()  local
111 	low = vioapic->rtbl[pin].reg;  in vioapic_send_intr()
112 	high = vioapic->rtbl[pin].reg >> 32;  in vioapic_send_intr()
121 	level = low & IOART_TRGRLVL ? true : false;  in vioapic_send_intr()
122 	if (level) {  in vioapic_send_intr()
128 		vioapic->rtbl[pin].reg |= IOART_REM_IRR;  in vioapic_send_intr()
132 	dest = high >> APIC_ID_SHIFT;  in vioapic_send_intr()
138 	 * in the Extended Destination ID bits for the 15-bit  in vioapic_send_intr()
141 	dest |= ((high & APIC_EXT_ID_MASK) >> APIC_EXT_ID_SHIFT) << 8;  in vioapic_send_intr()
142 	vlapic_deliver_intr(vioapic->vm, level, dest, phys, delmode, vector);  in vioapic_send_intr()
157 	oldcnt = vioapic->rtbl[pin].acnt;  in vioapic_set_pinstate()
159 		vioapic->rtbl[pin].acnt++;  in vioapic_set_pinstate()
161 		vioapic->rtbl[pin].acnt--;  in vioapic_set_pinstate()
162 	newcnt = vioapic->rtbl[pin].acnt;  in vioapic_set_pinstate()
242  * Reset the vlapic's trigger-mode register to reflect the ioapic pin
250 	uint32_t low, high, dest;  in vioapic_update_tmr()  local
252 	bool level, phys;  in vioapic_update_tmr()  local
259 	 * Reset all vectors to be edge-triggered.  in vioapic_update_tmr()
263 		low = vioapic->rtbl[pin].reg;  in vioapic_update_tmr()
264 		high = vioapic->rtbl[pin].reg >> 32;  in vioapic_update_tmr()
266 		level = low & IOART_TRGRLVL ? true : false;  in vioapic_update_tmr()
267 		if (!level)  in vioapic_update_tmr()
271 		 * For a level-triggered 'pin' let the vlapic figure out if  in vioapic_update_tmr()
274 		 * TMR bit associated with this vector to level-triggered.  in vioapic_update_tmr()
279 		dest = high >> APIC_ID_SHIFT;  in vioapic_update_tmr()
293 		return (vioapic->id);  in vioapic_read()
296 		return (((REDIR_ENTRIES - 1) << MAXREDIRSHIFT) | 0x11);  in vioapic_read()
299 		return (vioapic->id);  in vioapic_read()
308 		pin = (regnum - IOAPIC_REDTBL) / 2;  in vioapic_read()
309 		if ((regnum - IOAPIC_REDTBL) % 2)  in vioapic_read()
314 		return (vioapic->rtbl[pin].reg >> rshift);  in vioapic_read()
332 		vioapic->id = data & APIC_ID_MASK;  in vioapic_write()
345 		pin = (regnum - IOAPIC_REDTBL) / 2;  in vioapic_write()
346 		if ((regnum - IOAPIC_REDTBL) % 2)  in vioapic_write()
351 		last = vioapic->rtbl[pin].reg;  in vioapic_write()
355 		vioapic->rtbl[pin].reg &= ~mask64 | RTBL_RO_BITS;  in vioapic_write()
356 		vioapic->rtbl[pin].reg |= data64 & ~RTBL_RO_BITS;  in vioapic_write()
359 		 * Switching from level to edge triggering will clear the IRR  in vioapic_write()
361 		 * interrupt when the IO-APIC doesn't support targeted EOI (see  in vioapic_write()
364 		if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGREDG &&  in vioapic_write()
365 		    (vioapic->rtbl[pin].reg & IOART_REM_IRR) != 0)  in vioapic_write()
366 			vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;  in vioapic_write()
369 		    pin, vioapic->rtbl[pin].reg);  in vioapic_write()
374 		 * to update their vlapic trigger-mode registers.  in vioapic_write()
376 		changed = last ^ vioapic->rtbl[pin].reg;  in vioapic_write()
379 			    "vlapic trigger-mode register", pin);  in vioapic_write()
381 			allvcpus = vm_active_cpus(vioapic->vm);  in vioapic_write()
389 		 * - pin trigger mode is level  in vioapic_write()
390 		 * - pin level is asserted  in vioapic_write()
392 		if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGRLVL &&  in vioapic_write()
393 		    (vioapic->rtbl[pin].acnt > 0)) {  in vioapic_write()
395 			    "write, acnt %d", pin, vioapic->rtbl[pin].acnt);  in vioapic_write()
407 	offset = gpa - VIOAPIC_BASE;  in vioapic_mmio_rw()
410 	 * The IOAPIC specification allows 32-bit wide accesses to the  in vioapic_mmio_rw()
422 			*data = vioapic->ioregsel;  in vioapic_mmio_rw()
424 			vioapic->ioregsel = *data;  in vioapic_mmio_rw()
428 			    vioapic->ioregsel);  in vioapic_mmio_rw()
430 			vioapic_write(vioapic, vcpu, vioapic->ioregsel,  in vioapic_mmio_rw()
481 		if ((vioapic->rtbl[pin].reg & IOART_REM_IRR) == 0)  in vioapic_process_eoi()
483 		if ((vioapic->rtbl[pin].reg & IOART_INTVEC) != vector)  in vioapic_process_eoi()
485 		vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;  in vioapic_process_eoi()
486 		if (vioapic->rtbl[pin].acnt > 0) {  in vioapic_process_eoi()
488 			    "acnt %d", pin, vioapic->rtbl[pin].acnt);  in vioapic_process_eoi()
503 	vioapic->vm = vm;  in vioapic_init()
504 	mtx_init(&vioapic->mtx, "vioapic lock", NULL, MTX_SPIN);  in vioapic_init()
508 		vioapic->rtbl[i].reg = 0x0001000000010000UL;  in vioapic_init()
517 	mtx_destroy(&vioapic->mtx);  in vioapic_cleanup()
535 	SNAPSHOT_VAR_OR_LEAVE(vioapic->ioregsel, meta, ret, done);  in vioapic_snapshot()
537 	for (i = 0; i < nitems(vioapic->rtbl); i++) {  in vioapic_snapshot()
538 		SNAPSHOT_VAR_OR_LEAVE(vioapic->rtbl[i].reg, meta, ret, done);  in vioapic_snapshot()
539 		SNAPSHOT_VAR_OR_LEAVE(vioapic->rtbl[i].acnt, meta, ret, done);  in vioapic_snapshot()