1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
69  * and what bits should be set to zero in 'zeros_mask'. The don't-care
74  * Returns zero on success and non-zero on error.
150 		byte = 1024 + (msr - 0xC0000000) / 8;  in msr_bitmap_change_access()
285 	 * The register definition is based on the micro-architecture  in vmx_msr_init()
286 	 * but the following bits are always the same:  in vmx_msr_init()
287 	 * [15:8]  Maximum Non-Turbo Ratio  in vmx_msr_init()
288 	 * [28]    Programmable Ratio Limit for Turbo Mode  in vmx_msr_init()
289 	 * [29]    Programmable TDC-TDP Limit for Turbo Mode  in vmx_msr_init()
293 	 * micro-architectures up to Haswell.  in vmx_msr_init()
299 	 * dependent on the maximum cores per package supported by the micro-  in vmx_msr_init()
318 	if (vcpu->vcpuid == 0) {  in vmx_msr_guest_init()
329 	vcpu->guest_msrs[IDX_MSR_PAT] = PAT_VALUE(0, PAT_WRITE_BACK) |  in vmx_msr_guest_init()
347 	wrmsr(MSR_LSTAR, vcpu->guest_msrs[IDX_MSR_LSTAR]);  in vmx_msr_guest_enter()
348 	wrmsr(MSR_CSTAR, vcpu->guest_msrs[IDX_MSR_CSTAR]);  in vmx_msr_guest_enter()
349 	wrmsr(MSR_STAR, vcpu->guest_msrs[IDX_MSR_STAR]);  in vmx_msr_guest_enter()
350 	wrmsr(MSR_SF_MASK, vcpu->guest_msrs[IDX_MSR_SF_MASK]);  in vmx_msr_guest_enter()
351 	wrmsr(MSR_KGSBASE, vcpu->guest_msrs[IDX_MSR_KGSBASE]);  in vmx_msr_guest_enter()
357 	uint64_t guest_tsc_aux = vcpu->guest_msrs[IDX_MSR_TSC_AUX];  in vmx_msr_guest_enter_tsc_aux()
369 	vcpu->guest_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);  in vmx_msr_guest_exit()
370 	vcpu->guest_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);  in vmx_msr_guest_exit()
371 	vcpu->guest_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);  in vmx_msr_guest_exit()
372 	vcpu->guest_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);  in vmx_msr_guest_exit()
373 	vcpu->guest_msrs[IDX_MSR_KGSBASE] = rdmsr(MSR_KGSBASE);  in vmx_msr_guest_exit()
387 	uint64_t guest_tsc_aux = vcpu->guest_msrs[IDX_MSR_TSC_AUX];  in vmx_msr_guest_exit_tsc_aux()
393 		 * here; vcpu->guest_msrs[IDX_MSR_TSC_AUX] always  in vmx_msr_guest_exit_tsc_aux()
418 	case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1:  in vmx_rdmsr()
419 		if (vm_rdmtrr(&vcpu->mtrr, num, val) != 0) {  in vmx_rdmsr()
420 			vm_inject_gp(vcpu->vcpu);  in vmx_rdmsr()
434 		*val = vcpu->guest_msrs[IDX_MSR_PAT];  in vmx_rdmsr()
460 	case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1:  in vmx_wrmsr()
461 		if (vm_wrmtrr(&vcpu->mtrr, num, val) != 0) {  in vmx_wrmsr()
462 			vm_inject_gp(vcpu->vcpu);  in vmx_wrmsr()
487 			vcpu->guest_msrs[IDX_MSR_PAT] = val;  in vmx_wrmsr()
489 			vm_inject_gp(vcpu->vcpu);  in vmx_wrmsr()
492 		error = vmx_set_tsc_offset(vcpu, val - rdtsc());  in vmx_wrmsr()
501 			vcpu->guest_msrs[IDX_MSR_TSC_AUX] = val;  in vmx_wrmsr()
503 			vm_inject_gp(vcpu->vcpu);  in vmx_wrmsr()