Lines Matching +full:0 +full:x278
40 #define VMCB_CR_INTCPT 0
47 #define VMCB_INTCPT_INTR BIT(0)
81 #define VMCB_INTCPT_VMRUN BIT(0)
97 #define VMCB_TLB_FLUSH_NOTHING 0 /* Flush nothing */
103 #define VMCB_CACHE_NONE 0 /* No caching */
104 #define VMCB_CACHE_I BIT(0) /* Intercept, TSC off, Pause filter */
121 #define VMCB_EVENTINJ_TYPE_INTR 0
127 #define VMCB_EXIT_MC 0x52
128 #define VMCB_EXIT_INTR 0x60
129 #define VMCB_EXIT_NMI 0x61
130 #define VMCB_EXIT_VINTR 0x64
131 #define VMCB_EXIT_PUSHF 0x70
132 #define VMCB_EXIT_POPF 0x71
133 #define VMCB_EXIT_CPUID 0x72
134 #define VMCB_EXIT_IRET 0x74
135 #define VMCB_EXIT_INVD 0x76
136 #define VMCB_EXIT_PAUSE 0x77
137 #define VMCB_EXIT_HLT 0x78
138 #define VMCB_EXIT_INVLPGA 0x7A
139 #define VMCB_EXIT_IO 0x7B
140 #define VMCB_EXIT_MSR 0x7C
141 #define VMCB_EXIT_SHUTDOWN 0x7F
142 #define VMCB_EXIT_VMRUN 0x80
143 #define VMCB_EXIT_VMMCALL 0x81
144 #define VMCB_EXIT_VMLOAD 0x82
145 #define VMCB_EXIT_VMSAVE 0x83
146 #define VMCB_EXIT_STGI 0x84
147 #define VMCB_EXIT_CLGI 0x85
148 #define VMCB_EXIT_SKINIT 0x86
149 #define VMCB_EXIT_ICEBP 0x88
150 #define VMCB_EXIT_WBINVD 0x89
151 #define VMCB_EXIT_MONITOR 0x8A
152 #define VMCB_EXIT_MWAIT 0x8B
153 #define VMCB_EXIT_NPF 0x400
160 #define VMCB_NPF_INFO1_P BIT(0) /* Nested page present. */
173 #define VMCB_EXITINTINFO_VECTOR(x) ((x) & 0xFF)
174 #define VMCB_EXITINTINFO_TYPE(x) (((x) >> 8) & 0x7)
175 #define VMCB_EXITINTINFO_EC_VALID(x) (((x) & BIT(11)) ? 1 : 0)
176 #define VMCB_EXITINTINFO_VALID(x) (((x) & BIT(31)) ? 1 : 0)
177 #define VMCB_EXITINTINFO_EC(x) (((x) >> 32) & 0xFFFFFFFF)
181 #define VMCB_OFF_STATE(x) ((x) + 0x400)
183 #define VMCB_OFF_CR_INTERCEPT VMCB_OFF_CTRL(0x0)
184 #define VMCB_OFF_DR_INTERCEPT VMCB_OFF_CTRL(0x4)
185 #define VMCB_OFF_EXC_INTERCEPT VMCB_OFF_CTRL(0x8)
186 #define VMCB_OFF_INST1_INTERCEPT VMCB_OFF_CTRL(0xC)
187 #define VMCB_OFF_INST2_INTERCEPT VMCB_OFF_CTRL(0x10)
188 #define VMCB_OFF_PAUSE_FILTHRESH VMCB_OFF_CTRL(0x3C)
189 #define VMCB_OFF_PAUSE_FILCNT VMCB_OFF_CTRL(0x3E)
190 #define VMCB_OFF_IO_PERM VMCB_OFF_CTRL(0x40)
191 #define VMCB_OFF_MSR_PERM VMCB_OFF_CTRL(0x48)
192 #define VMCB_OFF_TSC_OFFSET VMCB_OFF_CTRL(0x50)
193 #define VMCB_OFF_ASID VMCB_OFF_CTRL(0x58)
194 #define VMCB_OFF_TLB_CTRL VMCB_OFF_CTRL(0x5C)
195 #define VMCB_OFF_VIRQ VMCB_OFF_CTRL(0x60)
196 #define VMCB_OFF_EXIT_REASON VMCB_OFF_CTRL(0x70)
197 #define VMCB_OFF_EXITINFO1 VMCB_OFF_CTRL(0x78)
198 #define VMCB_OFF_EXITINFO2 VMCB_OFF_CTRL(0x80)
199 #define VMCB_OFF_EXITINTINFO VMCB_OFF_CTRL(0x88)
200 #define VMCB_OFF_NP_ENABLE VMCB_OFF_CTRL(0x90)
201 #define VMCB_OFF_AVIC_BAR VMCB_OFF_CTRL(0x98)
202 #define VMCB_OFF_NPT_BASE VMCB_OFF_CTRL(0xB0)
203 #define VMCB_OFF_AVIC_PAGE VMCB_OFF_CTRL(0xE0)
204 #define VMCB_OFF_AVIC_LT VMCB_OFF_CTRL(0xF0)
205 #define VMCB_OFF_AVIC_PT VMCB_OFF_CTRL(0xF8)
207 #define VMCB_OFF_CPL VMCB_OFF_STATE(0xCB)
208 #define VMCB_OFF_STAR VMCB_OFF_STATE(0x200)
209 #define VMCB_OFF_LSTAR VMCB_OFF_STATE(0x208)
210 #define VMCB_OFF_CSTAR VMCB_OFF_STATE(0x210)
211 #define VMCB_OFF_SFMASK VMCB_OFF_STATE(0x218)
212 #define VMCB_OFF_KERNELGBASE VMCB_OFF_STATE(0x220)
213 #define VMCB_OFF_SYSENTER_CS VMCB_OFF_STATE(0x228)
214 #define VMCB_OFF_SYSENTER_ESP VMCB_OFF_STATE(0x230)
215 #define VMCB_OFF_SYSENTER_EIP VMCB_OFF_STATE(0x238)
216 #define VMCB_OFF_GUEST_PAT VMCB_OFF_STATE(0x268)
217 #define VMCB_OFF_DBGCTL VMCB_OFF_STATE(0x270)
218 #define VMCB_OFF_BR_FROM VMCB_OFF_STATE(0x278)
219 #define VMCB_OFF_BR_TO VMCB_OFF_STATE(0x280)
220 #define VMCB_OFF_INT_FROM VMCB_OFF_STATE(0x288)
221 #define VMCB_OFF_INT_TO VMCB_OFF_STATE(0x290)
226 #define VMCB_ACCESS(o, w) (0x80000000 | (((w) & 0xF) << 16) | \
227 ((o) & 0xFFF))
228 #define VMCB_ACCESS_OK(v) ((v) & 0x80000000 )
229 #define VMCB_ACCESS_BYTES(v) (((v) >> 16) & 0xF)
230 #define VMCB_ACCESS_OFFSET(v) ((v) & 0xFFF)
260 uint8_t pad1[0x28]; /* Offsets 0x14-0x3B are reserved. */
261 uint16_t pause_filthresh; /* Offset 0x3C, PAUSE filter threshold */
262 uint16_t pause_filcnt; /* Offset 0x3E, PAUSE filter count */
263 uint64_t iopm_base_pa; /* 0x40: IOPM_BASE_PA */
264 uint64_t msrpm_base_pa; /* 0x48: MSRPM_BASE_PA */
265 uint64_t tsc_offset; /* 0x50: TSC_OFFSET */
266 uint32_t asid; /* 0x58: Guest ASID */
267 uint8_t tlb_ctrl; /* 0x5C: TLB_CONTROL */
268 uint8_t pad2[3]; /* 0x5D-0x5F: Reserved. */
269 uint8_t v_tpr; /* 0x60: V_TPR, guest CR8 */
272 uint8_t v_intr_prio:4; /* 0x62: Priority for virtual interrupt. */
277 uint8_t v_intr_vector; /* 0x64: Vector for virtual interrupt. */
278 uint8_t pad3[3]; /* 0x65-0x67 Reserved. */
279 uint64_t intr_shadow:1; /* 0x68: Interrupt shadow, section15.2.1 APM2 */
281 uint64_t exitcode; /* 0x70, Exitcode */
282 uint64_t exitinfo1; /* 0x78, EXITINFO1 */
283 uint64_t exitinfo2; /* 0x80, EXITINFO2 */
284 uint64_t exitintinfo; /* 0x88, Interrupt exit value. */
285 uint64_t np_enable:1; /* 0x90, Nested paging enable. */
287 uint8_t pad4[0x10]; /* 0x98-0xA7 reserved. */
288 uint64_t eventinj; /* 0xA8, Event injection. */
292 uint32_t vmcb_clean; /* 0xC0: VMCB clean bits for caching */
293 uint32_t :32; /* 0xC4: Reserved */
294 uint64_t nrip; /* 0xC8: Guest next nRIP. */
295 uint8_t inst_len; /* 0xD0: #NPF decode assist */
297 uint8_t padd6[0x320];
312 uint8_t pad1[0x2b]; /* Reserved: 0xA0-0xCA */
316 uint8_t pad3[0x70]; /* Reserved: 0xd8-0x147 */
324 uint8_t pad4[0x58]; /* Reserved: 0x180-0x1D7 */
326 uint8_t pad5[0x18]; /* Reserved 0x1E0-0x1F7 */
337 uint8_t pad6[0x20];
344 uint8_t pad7[0x968]; /* Reserved up to end of VMCB */
346 CTASSERT(sizeof(struct vmcb_state) == 0xC00);
353 CTASSERT(offsetof(struct vmcb, state) == 0x400);