Lines Matching +full:0 +full:x8000000a
80 * SVM CPUID function 0x8000_000A, edx bit decoding.
82 #define AMD_CPUID_SVM_NP BIT(0) /* Nested paging or RVI */
107 0, NULL);
112 static uint32_t svm_feature = ~0U; /* AMD SVM features. */
113 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, features, CTLFLAG_RDTUN, &svm_feature, 0,
118 &disable_npf_assist, 0, NULL);
122 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, num_asids, CTLFLAG_RDTUN, &nasid, 0,
174 return (0); in svm_modcleanup()
186 do_cpuid(0x8000000A, regs); in check_svm_features()
193 if (nasid == 0 || nasid > regs[1]) in check_svm_features()
209 return (0); in check_svm_features()
225 * Return 1 if SVM is enabled on this processor and 0 otherwise.
233 if ((amd_feature2 & AMDID2_SVM) == 0) { in svm_available()
235 return (0); in svm_available()
239 if ((msr & VM_CR_SVMDIS) != 0) { in svm_available()
241 return (0); in svm_available()
261 for (cpu = 0; cpu < MAXCPU; cpu++) { in svm_modinit()
268 asid[cpu].gen = ~0UL; in svm_modinit()
279 return (0); in svm_modinit()
311 #define MSR_PENTIUM_START 0
312 #define MSR_PENTIUM_END 0x1FFF
314 #define MSR_AMD6TH_START 0xC0000000UL
315 #define MSR_AMD6TH_END 0xC0001FFFUL
317 #define MSR_AMD7TH_START 0xC0010000UL
318 #define MSR_AMD7TH_END 0xC0011FFFUL
328 KASSERT(error == 0, ("%s: vmcb_seg error %d", __func__, error)); in svm_get_cs_info()
333 *cs_d = 0; in svm_get_cs_info()
341 *base = 0; in svm_get_cs_info()
342 *cs_d = 0; in svm_get_cs_info()
358 base = 0; in svm_msr_index()
362 return (0); in svm_msr_index()
369 return (0); in svm_msr_index()
376 return (0); in svm_msr_index()
391 KASSERT(error == 0, ("%s: invalid msr %#lx", __func__, msr)); in svm_msr_perm()
392 KASSERT(index >= 0 && index < SVM_MSR_BITMAP_SIZE, in svm_msr_perm()
394 KASSERT(bit >= 0 && bit <= 6, ("%s: invalid bit position %d " in svm_msr_perm()
423 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); in svm_get_intercept()
426 return (ctrl->intercept[idx] & bitmask ? 1 : 0); in svm_get_intercept()
435 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); in svm_set_intercept()
456 svm_set_intercept(vcpu, off, bitmask, 0); in svm_disable_intercept()
489 for (n = 0; n < 16; n++) { in vmcb_init()
491 if (n == 0 || n == 2 || n == 3 || n == 4 || n == 8) in vmcb_init()
502 for (n = 0; n < 32; n++) { in vmcb_init()
555 ctrl->asid = 0; in vmcb_init()
567 state->dbgctl = BIT(0); in vmcb_init()
573 state->g_pat = PAT_VALUE(0, PAT_WRITE_BACK) | in vmcb_init()
598 M_WAITOK, 0, ~(vm_paddr_t)0, PAGE_SIZE, 0); in svm_init()
602 M_WAITOK, 0, ~(vm_paddr_t)0, PAGE_SIZE, 0); in svm_init()
612 memset(svm_sc->msr_bitmap, 0xFF, SVM_MSR_BITMAP_SIZE); in svm_init()
640 memset(svm_sc->iopm_bitmap, 0xFF, SVM_IO_BITMAP_SIZE); in svm_init()
657 vcpu->nextrip = ~0; in svm_vcpu_init()
702 KASSERT(error == 0, ("%s: vmcb_seg(cs) error %d", __func__, in svm_vcpu_mode()
724 if ((cr0 & CR0_PG) == 0) in svm_paging_mode()
726 if ((cr4 & CR4_PAE) == 0) in svm_paging_mode()
773 s = (info1 >> 10) & 0x7; in svm_inout_str_seginfo()
791 KASSERT(error == 0, ("%s: svm_getdesc error %d", __func__, error)); in svm_inout_str_seginfo()
799 size = (info1 >> 7) & 0x7; in svm_inout_str_addrsize()
825 #define UNHANDLED 0
845 inout_string = info1 & BIT(2) ? 1 : 0; in svm_handle_io()
848 vmexit->u.inout.in = (info1 & BIT(0)) ? 1 : 0; in svm_handle_io()
850 vmexit->u.inout.rep = (info1 & BIT(3)) ? 1 : 0; in svm_handle_io()
851 vmexit->u.inout.bytes = (info1 >> 4) & 0x7; in svm_handle_io()
864 vis->cs_d = 0; in svm_handle_io()
865 vis->cs_base = 0; in svm_handle_io()
896 if ((exitinfo1 & VMCB_NPF_INFO1_GPA) == 0) { in svm_npf_emul_fault()
929 inst_len = 0; in svm_handle_inst_emul()
965 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, in svm_eventinject()
968 KASSERT(vector >=0 && vector <= 255, ("%s: invalid vector %d", in svm_eventinject()
977 if (vector >= 0 && vector <= 31 && vector != 2) in svm_eventinject()
1009 KASSERT(ctrl->v_intr_vector == 0, ("%s: invalid " in svm_update_virqinfo()
1030 SVM_CTR2(vcpu, "SVM:Pending INTINFO(0x%lx), vector=%d.\n", intinfo, in svm_save_intinfo()
1052 if (ctrl->v_irq && ctrl->v_intr_vector == 0) { in enable_intr_window_exiting()
1062 ctrl->v_intr_vector = 0; in enable_intr_window_exiting()
1074 if (!ctrl->v_irq && ctrl->v_intr_vector == 0) { in disable_intr_window_exiting()
1081 ctrl->v_irq = 0; in disable_intr_window_exiting()
1082 ctrl->v_intr_vector = 0; in disable_intr_window_exiting()
1095 newval = val ? 1 : 0; in svm_modify_intr_shadow()
1100 return (0); in svm_modify_intr_shadow()
1110 return (0); in svm_get_intr_shadow()
1164 #define EFER_MBZ_BITS 0xFFFFFFFFFFFF0200UL
1180 newval &= ~0xFE; /* clear the Read-As-Zero (RAZ) bits */ in svm_write_efer()
1193 if ((newval & EFER_LME) != 0 && (state->cr0 & CR0_PG) != 0) in svm_write_efer()
1196 lma = 0; in svm_write_efer()
1212 vm_exit_svm(vme, VMCB_EXIT_MSR, 1, 0); in svm_write_efer()
1214 return (0); in svm_write_efer()
1228 KASSERT(error == 0, ("%s: error %d updating efer", __func__, error)); in svm_write_efer()
1229 return (0); in svm_write_efer()
1232 return (0); in svm_write_efer()
1264 if (error == 0) { in emulate_rdmsr()
1267 state->rax = result & 0xffffffff; in emulate_rdmsr()
1313 for (i = 0; i < nitems(reasons); i++) { in exit_reason_to_str()
1327 * Return 1 if the nRIP is valid and 0 otherwise.
1333 case 0x00 ... 0x0F: /* read of CR0 through CR15 */ in nrip_valid()
1334 case 0x10 ... 0x1F: /* write of CR0 through CR15 */ in nrip_valid()
1335 case 0x20 ... 0x2F: /* read of DR0 through DR15 */ in nrip_valid()
1336 case 0x30 ... 0x3F: /* write of DR0 through DR15 */ in nrip_valid()
1337 case 0x43: /* INT3 */ in nrip_valid()
1338 case 0x44: /* INTO */ in nrip_valid()
1339 case 0x45: /* BOUND */ in nrip_valid()
1340 case 0x65 ... 0x7C: /* VMEXIT_CR0_SEL_WRITE ... VMEXIT_MSR */ in nrip_valid()
1341 case 0x80 ... 0x8D: /* VMEXIT_VMRUN ... VMEXIT_XSETBV */ in nrip_valid()
1344 return (0); in nrip_valid()
1366 handled = 0; in svm_vmexit()
1373 vmexit->inst_length = nrip_valid(code) ? ctrl->nrip - state->rip : 0; in svm_vmexit()
1384 return (0); in svm_vmexit()
1387 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, ("%s: event " in svm_vmexit()
1390 KASSERT(vmexit->inst_length >= 0 && vmexit->inst_length <= 15, in svm_vmexit()
1402 vmexit->inst_length = 0; in svm_vmexit()
1417 case 0x40 ... 0x5F: in svm_vmexit()
1420 idtvec = code - 0x40; in svm_vmexit()
1427 reflect = 0; in svm_vmexit()
1433 KASSERT(error == 0, ("%s: error %d updating cr2", in svm_vmexit()
1446 info1 = 0; in svm_vmexit()
1453 bool stepped = 0; in svm_vmexit()
1454 uint64_t dr6 = 0; in svm_vmexit()
1461 vmexit->u.dbg.pushf_intercept = 0; in svm_vmexit()
1470 vcpu->dbg.popf_sstep = 0; in svm_vmexit()
1474 * setcap(..., RFLAGS_SSTEP, 0) restores in svm_vmexit()
1485 vcpu->dbg.pushf_sstep = 0; in svm_vmexit()
1503 KASSERT(error == 0, in svm_vmexit()
1507 reflect = 0; in svm_vmexit()
1514 vmexit->inst_length = 0; in svm_vmexit()
1516 reflect = 0; in svm_vmexit()
1532 vmexit->inst_length = 0; in svm_vmexit()
1535 errcode_valid = 0; in svm_vmexit()
1536 info1 = 0; in svm_vmexit()
1541 KASSERT(vmexit->inst_length == 0, in svm_vmexit()
1549 errcode_valid, info1, 0); in svm_vmexit()
1550 KASSERT(error == 0, ("%s: vm_inject_exception error %d", in svm_vmexit()
1643 vmexit->inst_length = 0; in svm_vmexit()
1646 VMCB_INTCPT_PUSHF, 0); in svm_vmexit()
1662 vmexit->inst_length = 0; in svm_vmexit()
1665 VMCB_INTCPT_POPF, 0); in svm_vmexit()
1702 vmexit->inst_length = 0; in svm_vmexit()
1760 need_intr_window = 0; in svm_inj_interrupts()
1763 ctrl->intr_shadow = 0; in svm_inj_interrupts()
1821 IDT_NMI, 0, false); in svm_inj_interrupts()
1839 KASSERT(vector >= 0 && vector <= 255, in svm_inj_interrupts()
1847 if ((state->rflags & PSL_I) == 0) { in svm_inj_interrupts()
1868 svm_eventinject(vcpu, VMCB_EVENTINJ_TYPE_INTR, vector, 0, false); in svm_inj_interrupts()
1915 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) != 0 || in svm_inj_interrupts()
1916 (state->rflags & PSL_I) == 0 || ctrl->intr_shadow, in svm_inj_interrupts()
1972 * 0 0 (a) in svm_pmap_activate()
1973 * 0 1 (b1) or (b2) in svm_pmap_activate()
1974 * 1 0 (c) in svm_pmap_activate()
2015 if (++asid[cpu].gen == 0) in svm_pmap_activate()
2041 KASSERT(ctrl->asid != 0, ("Guest ASID must be non-zero")); in svm_pmap_activate()
2081 load_dr7(0); in svm_dr_enter_guest()
2082 wrmsr(MSR_DEBUGCTLMSR, 0); in svm_dr_enter_guest()
2152 vcpu->asid.gen = 0; in svm_run()
2157 svm_set_dirty(vcpu, 0xffffffff); in svm_run()
2237 vcpu->dirty = 0; in svm_run()
2270 return (0); in svm_run()
2350 if (vmcb_read(vcpu, ident, val) == 0) { in svm_getreg()
2351 return (0); in svm_getreg()
2358 return (0); in svm_getreg()
2379 if (vmcb_write(vcpu, ident, val) == 0) { in svm_setreg()
2380 return (0); in svm_setreg()
2388 return (0); in svm_setreg()
2393 return (0); in svm_setreg()
2427 if (ret != 0) in svm_snapshot_reg()
2435 if (ret != 0) in svm_snapshot_reg()
2455 error = 0; in svm_setcap()
2468 if (val == 0) in svm_setcap()
2508 vcpu->dbg.rflags_tf = 0; in svm_setcap()
2541 error = 0; in svm_getcap()
2623 err = 0; in svm_vcpu_snapshot()
2771 if (err != 0) in svm_vcpu_snapshot()
2813 svm_set_dirty(vcpu, 0xffffffff); in svm_vcpu_snapshot()
2826 return (0); in svm_restore_tsc()