1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
53 		    int reg, int bytes);
56 		    unsigned slot, unsigned func, unsigned reg, unsigned bytes);
58 		    unsigned slot, unsigned func, unsigned reg, int data,
60 static int	pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
61 static void	pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
66  * For amd64 we assume that type 1 I/O port-based access always works.
68  * switch to memory-mapped access.
80     "Enable support for PCI-e memory mapped config access");
101 pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)  in pci_docfgregread()  argument
104 		return (pcireg_cfgread(bus, slot, func, reg, bytes));  in pci_docfgregread()
111 			return (pciereg_cfgread(region, bus, slot, func, reg,  in pci_docfgregread()
116 		return (pcireg_cfgread(bus, slot, func, reg, bytes));  in pci_docfgregread()
118 		return (-1);  in pci_docfgregread()
125 pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)  in pci_cfgregread()  argument
132 	 * numbers in the range 128-254 to indicate something strange and  in pci_cfgregread()
137 	if (reg == PCIR_INTLINE && bytes == 1) {  in pci_cfgregread()
144 	return (pci_docfgregread(domain, bus, slot, func, reg, bytes));  in pci_cfgregread()
151 pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,  in pci_cfgregwrite()  argument
155 		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);  in pci_cfgregwrite()
164 			pciereg_cfgwrite(region, bus, slot, func, reg, data,  in pci_cfgregwrite()
171 		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);  in pci_cfgregwrite()
178 /* enable configuration space accesses and return data port address */
180 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)  in pci_cfgenable()  argument
185 	    (unsigned)reg <= PCI_REGMAX && bytes != 3 &&  in pci_cfgenable()
186 	    (unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {  in pci_cfgenable()
188 		    | (func << 8) | (reg & ~0x03));  in pci_cfgenable()
189 		dataport = CONF1_DATA_PORT + (reg & 0x03);  in pci_cfgenable()
206 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)  in pcireg_cfgread()  argument
208 	int data = -1;  in pcireg_cfgread()  local
212 	port = pci_cfgenable(bus, slot, func, reg, bytes);  in pcireg_cfgread()
216 			data = inb(port);  in pcireg_cfgread()
219 			data = inw(port);  in pcireg_cfgread()
222 			data = inl(port);  in pcireg_cfgread()
228 	return (data);  in pcireg_cfgread()
232 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)  in pcireg_cfgwrite()  argument
237 	port = pci_cfgenable(bus, slot, func, reg, bytes);  in pcireg_cfgwrite()
241 			outb(port, data);  in pcireg_cfgwrite()
244 			outw(port, data);  in pcireg_cfgwrite()
247 			outl(port, data);  in pcireg_cfgwrite()
263 	 * inaccessible using memory-mapped PCI config access.  Walk  in pcie_init_badslots()
289 		printf("PCI: MCFG domain %u bus %u-%u base @ 0x%lx\n",  in pcie_cfgregopen()
299 	region->base = pmap_mapdev_pciecfg(base + (minbus << 20), (maxbus + 1 - minbus) << 20);  in pcie_cfgregopen()
300 	region->domain = domain;  in pcie_cfgregopen()
301 	region->minbus = minbus;  in pcie_cfgregopen()
302 	region->maxbus = maxbus;  in pcie_cfgregopen()
313 #define PCIE_VADDR(base, reg, bus, slot, func)	\  argument
318 	((reg) & 0xfff)))
330     unsigned func, unsigned reg, unsigned bytes)  in pciereg_cfgread()  argument
333 	int data = -1;  in pciereg_cfgread()  local
335 	MPASS(bus >= region->minbus && bus <= region->maxbus);  in pciereg_cfgread()
337 	if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)  in pciereg_cfgread()
338 		return (-1);  in pciereg_cfgread()
340 	va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);  in pciereg_cfgread()
344 		__asm("movl %1, %0" : "=a" (data)  in pciereg_cfgread()
348 		__asm("movzwl %1, %0" : "=a" (data)  in pciereg_cfgread()
352 		__asm("movzbl %1, %0" : "=a" (data)  in pciereg_cfgread()
357 	return (data);  in pciereg_cfgread()
362     unsigned func, unsigned reg, int data, unsigned bytes)  in pciereg_cfgwrite()  argument
366 	MPASS(bus >= region->minbus && bus <= region->maxbus);  in pciereg_cfgwrite()
368 	if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)  in pciereg_cfgwrite()
371 	va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);  in pciereg_cfgwrite()
376 		    : "a" (data));  in pciereg_cfgwrite()
380 		    : "a" ((uint16_t)data));  in pciereg_cfgwrite()
384 		    : "a" ((uint8_t)data));  in pciereg_cfgwrite()