Lines Matching full:pci
2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,
3 and DMA interfaces that a driver uses to access its PCI controller.
23 /// Global ID for the PCI I/O Protocol
52 // Complete PCI address generater
64 #define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI…
65 …O_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header
66 #define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config…
69 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
70 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM …
71 #define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can n…
108 /// Retrieve the PCI controller's current attributes, and return them in Result.
112 /// Set the PCI controller's current attributes to Attributes.
116 …/// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.
120 …/// Disable the attributes specified by the bits that are set in Attributes for this PCI controlle…
124 /// Retrieve the PCI controller's supported attributes, and return them in Result.
131 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
136 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
145 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
146 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
166 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
170 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
177 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
178 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
180 valid for the PCI BAR specified by BarIndex.
198 /// Read PCI controller registers in the PCI memory or I/O space.
202 /// Write PCI controller registers in the PCI memory or I/O space.
208 Enable a PCI driver to access PCI controller registers in PCI configuration space.
212 …@param Offset The offset within the PCI configuration space for the PCI controller.
213 @param Count The number of PCI configuration operations to perform.
218 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
220 valid for the PCI configuration header of the PCI controller.
237 /// Read PCI controller registers in PCI configuration space.
241 /// Write PCI controller registers in PCI configuration space.
247 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
252 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
256 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
264 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
265 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
267 is not valid for the PCI BAR specified by DestBarIndex.
269 not valid for the PCI BAR specified by SrcBarIndex.
287 Provides the PCI controller-specific addresses needed to access system memory.
291 @param HostAddress The system memory address to map to the PCI controller.
294 …@param DeviceAddress The resulting map address for the bus master PCI controller to use to
385 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
389 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
391 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
402 Retrieves this PCI controller's current PCI bus number, device number, and function number.
405 @param SegmentNumber The PCI controller's current PCI segment number.
406 @param BusNumber The PCI controller's current PCI bus number.
407 @param DeviceNumber The PCI controller's current PCI device number.
408 @param FunctionNumber The PCI controller's current PCI function number.
410 …@retval EFI_SUCCESS The PCI controller location was returned. …
425 Performs an operation on the attributes that this PCI controller supports. The operations include
430 @param Operation The operation to perform on the attributes for this PCI controller.
436 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
439 Attributes are not supported by this PCI controller or one of
453 Gets the attributes that this PCI controller supports setting on a BAR using
457 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
459 …@param Supports A pointer to the mask of attributes that this PCI controller supports
462 … configuration of this BAR of the PCI controller.
464 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI
466 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
469 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
484 Sets the attributes for a range of a BAR on a PCI controller.
489 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
498 set on the PCI controller, and the actual resource range is returned
501 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
518 /// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,
519 /// and DMA interfaces used to abstract accesses to PCI controllers.
520 /// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.
521 /// A device driver that wishes to manage a PCI controller in a system will have to
522 /// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.
529 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci; member
547 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
549 /// The contents of this buffer are either from the PCI option ROM that can be accessed
550 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.