Lines Matching full:memory

163 Direct Memory Access (DMA) is a method of transferring data
165 A DMA transaction can be achieved between device to memory,
166 device to device, or memory to memory.
207 represents a mapping of a memory region for DMA.
214 a mapping must be bound to a memory region by calling one of the
222 engine to access the memory region.
232 the sync operations copy data between the bounce pages and the memory region
235 flushing and CPU memory operation ordering.
239 Static transactions are used with a long-lived memory region that is reused
247 Static transactions use memory regions allocated by
249 Each static memory region is allocated by calling
256 allocates a memory region along with a mapping object.
257 The associated tag, memory region, and mapping object must then be passed to
264 will attempt to allocate memory requiring less expensive sync operations
273 When a consumer is finished with a memory region,
276 and then release the memory region and mapping object via
279 Dynamic transactions map memory regions provided by other parts of the system.
282 to describe the DMA transactions to and from these memory regions,
287 When a consumer wishes to schedule a transaction for a memory region,
290 The memory region must be bound to the mapping object via one of the
294 the consumer should sync the memory region via
300 the consumer should sync the memory region via
397 One map is used for each memory allocation that will be loaded.
461 Memory synchronization operation specifier.
462 Bus DMA requires explicit synchronization of memory with its device
463 visible mapping in order to guarantee memory coherency.
475 All operations specified below are performed from the host memory point of view,
476 where a read implies data coming from the device to the host memory, and a write
477 implies data going from the host memory to the device.
484 Perform any synchronization required prior to an update of host memory by the
487 Perform any synchronization required after an update of host memory by the CPU
488 and prior to device access to host memory.
490 Perform any synchronization required after an update of host memory by the
491 device and prior to CPU access to host memory.
493 Perform any synchronization required after device access to host memory.
561 to honor restrictions between the parent bridge, CPU memory, and the
573 Boundary constraint, in bytes, of the target DMA memory region.
607 address space, overlapping available host memory, be outside the
610 .Ql safe memory
646 Cached memory may be used to back allocations created by
674 if sufficient memory is not available for tag creation
760 Attempt to map the memory loaded with this map such that cache sync
762 This flag is typically set on maps when the memory loaded with these will
777 if sufficient memory is not available for creating the
1011 User space memory must be in-core and wired prior to attempting a map
1033 memory referenced by that mapping.
1053 memory access (DMA) to shared
1054 memory is coherent.
1058 memory, the buffer must be loaded and a DMA sync operation of
1066 Conversely, suppose a device updates memory that is to be read by a CPU.
1070 The CPU will only be able to see the results of this memory update
1078 Allocates memory that is mapped into KVA at the address returned
1103 Attempt to map this memory in a coherent fashion.
1113 Causes the allocated memory to be set to all zeros.
1115 The allocated memory will not be cached in the processor caches.
1116 All memory accesses appear on the bus and are executed
1131 The size of memory to be allocated is
1143 memory, and an unload operation is required before freeing the memory, as
1149 Although an explicit load is not required for each access to the memory
1158 if sufficient memory is not available for completing
1161 Frees memory previously allocated by
1170 Kernel virtual address of the memory.
1250 due to memory or resource allocation.