Lines Matching full:loads
92 ordinary loads and stores of integers in cache-coherent memory are
95 However, such loads and stores may be elided from the program by
188 Conversely, acquire semantics do not require that prior loads or stores have
198 completed before any subsequent loads and stores are performed, use
201 When an atomic operation has release semantics, all prior loads or stores
212 For example, to add two long integers ensuring that all prior loads and
221 subsequent loads by the acquiring thread.
233 will prevent any loads or stores from moving outside of the critical
235 However, they will not prevent the compiler or processor from moving loads
244 When a fence has acquire semantics, all prior loads (by program order) must
252 When a fence has release semantics, all prior loads or stores (by program
269 Neither loads nor stores may cross this barrier in either direction.
278 aligned loads and stores, fences can also be synchronized by ordinary loads
286 imposed by fences must be more restrictive than acquire loads and release
290 Although fences impose more restrictive ordering than acquire loads and