Lines Matching +full:encode +full:- +full:only

1 .\" Copyright (c) 2016-2017 The FreeBSD Foundation.
32 .Nd Architecture-specific details
40 For full details consult the processor-specific ABI supplement
62 and no other types as these types are the only integer types where the
98 .Bl -column -offset indent "Architecture" "Initial Release"
111 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
142 .Bl -tag -width "Dv L64PC128"
149 types machine representations all have 4-byte size.
173 Typically these are 64-bit machines, where the
179 environment, which was the historical 32-bit predecessor for 64-bit evolution.
181 .Bl -column -offset indent "powerpc64" "ILP32 counterpart"
199 Architectures with 128-bit capabilities support both a
205 .Bl -column -offset indent "aarch64c" "LP64 counterpart"
212 .Bl -column -offset indent "long long" "Size"
226 requires only 4-byte alignment for 64-bit integers.
228 Machine-dependent type sizes:
229 .Bl -column -offset indent "Architecture" "long" "void *" "long double" "time_t"
247 .Bl -column -offset indent "Architecture" "Endianness" "char Signedness"
262 .Bl -column -offset indent "Architecture" "Page Sizes"
277 .Bl -column -offset indent "riscv64 (Sv48)" "0x0001000000000000" "NNNU"
300 Historically, amd64 CPUs were limited to a 48-bit virtual address space.
301 Newer CPUs support 5-level page tables, which extend the significant bits of
306 tunable to 0 forces the system into 4-level paging mode, even on hardware that
307 supports 5-level paging.
308 In this mode, all processes get a 48-bit address space.
312 a 48-bit address space by default.
323 The RISC-V specification permits 3-level (Sv39), 4-level (Sv48), and
324 5-level (Sv57) page tables.
325 Hardware is only required to implement Sv39; implementations which support
334 .Bl -column -offset indent "Architecture" "float, double" "long double"
371 .Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
382 Some of these provide architecture-specific details and are explained below.
387 .Bd -literal -offset indent
388 cc -x c -dM -E /dev/null
392 .Bl -column -offset indent "__SIZEOF_POINTER__" "Meaning"
397 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
398 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
399 .It Dv __CHERI__ Ta 128-bit (16-byte) capability pointer, 64-bit (8-byte) long
407 it has been common for programmers to test only one and assume the other
419 as their pointers are 128-bit capabilities.
421 Architecture-specific macros:
422 .Bl -column -offset indent "Architecture" "Predefined macros"
437 Compilers may define additional variants of architecture-specific macros.
446 .Bl -tag -width "MACHINE_CPUARCH"
455 It should only be used in these contexts.
470 of i386 supported the IBM-AT hardware platform while the
472 of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
474 Both of these hardware platforms supported only the
481 should only be used in src/sys and src/stand or in system imagers or
490 It may also encode a variation in the byte ordering of multi-byte
492 It may also encode a variation in the size of the integer or pointer.
493 It may also encode a ISA revision.
494 It may also encode hard versus soft floating point ABI and usage.
495 It may also encode a variant ABI when the other factors do not
504 If we ever were to support the so-called x32 ABI (using 32-bit
506 as amd64-x32.
507 It is unfortunate that amd64 specifies the 64-bit evolution of the x86 platform