Lines Matching +full:port +full:- +full:level

30 .Nd Parallel Port Bus system
42 system provides a uniform, modular and architecture-independent
44 and to utilize different parallel port chipsets.
46 In order to write new drivers or port existing drivers, the ppbus system
48 .Bl -bullet -offset indent
50 architecture-independent macros or functions to access parallel ports
52 mechanism to allow various devices to share the same parallel port
56 that allows parallel port access from outside the kernel without conflicting
57 with kernel-in drivers.
61 and non-standard software:
63 .Bl -column "Driver" -compact
65 .It Sy ppi Ta "Parallel port interface for general I/O"
67 .It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface"
70 Another approach to the ppbus system is to port existing drivers.
73 .Bl -column "Driver" -compact
79 ppbus should let you port any other software even from other operating systems
81 .Sh PARALLEL PORT CHIPSETS
82 Parallel port chipset support is provided by
86 parallel port bus, then initialize it and upper peripheral device drivers.
90 .Sh PARALLEL PORT MODEL
91 The logical parallel port model chosen for the ppbus system is the PC's
92 parallel port model.
99 The parallel port may operate in the following modes:
100 .Bl -bullet -offset indent
104 bidirectional 8/4-bits mode, also called NIBBLE mode
108 Extended Capability Port mode, ECP
110 Enhanced Parallel Port mode, EPP
116 In this mode, data is placed on the port's data lines, the printer status is
123 "Fast Centronics" or "Parallel Port FIFO mode".
130 In this mode, outputs are 8-bits long.
136 any transfer is 8-bits long.
137 .Ss Extended Capability Port mode
145 .Bl -item -offset indent
153 .Ss Enhanced Parallel Port mode
155 performance parallel port link that would still be compatible with the
156 standard parallel port.
160 difference at hardware level is the strobe of the byte placed on the data
167 In this fashion, parallel port peripherals can
168 operate at close to the same performance levels as an equivalent ISA plug-in
171 At software level, you may implement the protocol you wish, using data and
188 .Sh IEEE1284-1994 Standard
200 at signal level.
205 The IEEE1284 protocol is fully oriented with all supported parallel port
236 as a set of procedures that perform high level functions like negotiation,
237 termination, transfer in any mode without bothering you with low level
251 chipset abstraction throw a set of low level functions that maps the logical
257 .Bl -enum -offset indent
259 share the parallel port bus among the daisy-chain like connected devices
263 propose an arch-independent interface to access the hardware layer.
274 With this level of abstraction a particular chipset may commute from any
280 This architecture should support IEEE1284-1994 modes.
291 .%T "Plug and Play Parallel Port Devices"
292 draft from (c)1993-4 Microsoft Corporation)
302 usage of ppbus allocation is to reserve the port and receive incoming
305 High level interrupt handlers are connected to the ppbus system thanks to the
319 is a general purpose mechanism to allow fast low-level
320 manipulation of the parallel port.
322 standard (in IEEE1284 modes) or non-standard transfers.
325 the job at adapter level.
331 Standard I/O operations are implemented at ppbus level whereas basic I/O
332 operations and microseq language are coded at adapter level for efficiency.