Lines Matching +full:parallel +full:- +full:in

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30 .Nd Parallel Port Bus system
42 system provides a uniform, modular and architecture-independent
43 system for the implementation of drivers to control various parallel devices,
44 and to utilize different parallel port chipsets.
48 .Bl -bullet -offset indent
50 architecture-independent macros or functions to access parallel ports
52 mechanism to allow various devices to share the same parallel port
56 that allows parallel port access from outside the kernel without conflicting
57 with kernel-in drivers.
61 and non-standard software:
63 .Bl -column "Driver" -compact
65 .It Sy ppi Ta "Parallel port interface for general I/O"
67 .It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface"
73 .Bl -column "Driver" -compact
76 .It Sy plip Ta "lp parallel network interface driver"
81 .Sh PARALLEL PORT CHIPSETS
82 Parallel port chipset support is provided by
86 parallel port bus, then initialize it and upper peripheral device drivers.
90 .Sh PARALLEL PORT MODEL
91 The logical parallel port model chosen for the ppbus system is the PC's
92 parallel port model.
99 The parallel port may operate in the following modes:
100 .Bl -bullet -offset indent
104 bidirectional 8/4-bits mode, also called NIBBLE mode
110 Enhanced Parallel Port mode, EPP
123 "Fast Centronics" or "Parallel Port FIFO mode".
130 In this mode, outputs are 8-bits long.
136 any transfer is 8-bits long.
145 .Bl -item -offset indent
153 .Ss Enhanced Parallel Port mode
155 performance parallel port link that would still be compatible with the
156 standard parallel port.
166 EPP cycle fits in an ISA cycle.
167 In this fashion, parallel port peripherals can
168 operate at close to the same performance levels as an equivalent ISA plug-in
188 .Sh IEEE1284-1994 Standard
191 Bidirectional Parallel Peripheral Interface for Personal Computers".
194 parallel communications between hosts and printers or other peripherals.
201 One should refer to architecture specific documentation in
205 The IEEE1284 protocol is fully oriented with all supported parallel port
237 termination, transfer in any mode without bothering you with low level
257 .Bl -enum -offset indent
259 share the parallel port bus among the daisy-chain like connected devices
263 propose an arch-independent interface to access the hardware layer.
268 layer gathers the parallel peripheral device drivers.
269 .Ss Parallel modes management
280 This architecture should support IEEE1284-1994 modes.
290 ppbus attachment tries to detect any PnP parallel peripheral (according to
291 .%T "Plug and Play Parallel Port Devices"
292 draft from (c)1993-4 Microsoft Corporation)
297 This mode will be saved in the context structure and
311 But, in order to attach a handler, drivers must
313 Consequently, a ppbus request is mandatory in order to call the above
319 is a general purpose mechanism to allow fast low-level
320 manipulation of the parallel port.
322 standard (in IEEE1284 modes) or non-standard transfers.
329 operation (opcodes are described in
341 manual page first appeared in