Lines Matching +full:master +full:- +full:level

42 system provides a uniform, modular and architecture-independent
48 .Bl -bullet -offset indent
50 architecture-independent macros or functions to access parallel ports
57 with kernel-in drivers.
61 and non-standard software:
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67 .It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface"
73 .Bl -column "Driver" -compact
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104 bidirectional 8/4-bits mode, also called NIBBLE mode
130 In this mode, outputs are 8-bits long.
136 any transfer is 8-bits long.
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160 difference at hardware level is the strobe of the byte placed on the data
168 operate at close to the same performance levels as an equivalent ISA plug-in
171 At software level, you may implement the protocol you wish, using data and
188 .Sh IEEE1284-1994 Standard
200 at signal level.
207 The computer acts as master and the peripheral as slave.
227 But peripheral requests are only a hint to the master host.
236 as a set of procedures that perform high level functions like negotiation,
237 termination, transfer in any mode without bothering you with low level
251 chipset abstraction throw a set of low level functions that maps the logical
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259 share the parallel port bus among the daisy-chain like connected devices
263 propose an arch-independent interface to access the hardware layer.
274 With this level of abstraction a particular chipset may commute from any
280 This architecture should support IEEE1284-1994 modes.
292 draft from (c)1993-4 Microsoft Corporation)
305 High level interrupt handlers are connected to the ppbus system thanks to the
319 is a general purpose mechanism to allow fast low-level
322 standard (in IEEE1284 modes) or non-standard transfers.
325 the job at adapter level.
331 Standard I/O operations are implemented at ppbus level whereas basic I/O
332 operations and microseq language are coded at adapter level for efficiency.