Lines Matching +full:adc +full:- +full:dev

45 .Bd -literal
46 dev.ti_adc.0.%desc: TI ADC controller
48 dev.ti_adc.0.%pnpinfo: name=adc@44E0D000 compat=ti,adc
85 On Beaglebone-black the analog input 7 is connected to the 3V3B rail through
91 .Bl -tag -width ".Va dev.ti_adc.0.clockdiv"
92 .It Va dev.ti_adc.0.clockdiv
93 Sets the ADC clock prescaler.
95 The ADC clock is based on CLK_M_OSC (24Mhz) / clockdiv.
96 This gives a maximum of ~2.4Mhz for the ADC clock and ~10Khz for the default
101 .Bl -tag -width ".Va dev.ti_adc.0.ain.%d.samples_avg"
102 .It Va dev.ti_adc.0.ain.%d.enable
105 When all the inputs are disabled, the ADC is turned off.
106 .It Va dev.ti_adc.0.ain.%d.open_delay
107 Sets the number of ADC clock cycles to wait after applying the input
108 configuration and before start the ADC conversion.
109 .It Va dev.ti_adc.0.ain.%d.samples_avg
112 .It Va dev.ti_adc.0.ain.%d.input
124 .An -nosplit