Lines Matching +full:reset +full:- +full:on +full:- +full:timeout

21 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
51 support for the watchdog timer present on NXP i.MX5 and i.MX6 processors.
53 0.5 to 128 seconds, in half-second increments.
55 timeout period can be changed to any valid non-zero value.
57 At power-on, a special 16-second
58 .Sq power-down timer
61 external hardware that causes the system to reset or power-down.
62 The power-down timer is often reset by the boot loader (typically U-Boot).
63 If the power-down timer is still active at the time when the normal
71 .Va fsl,external-reset
72 property by enabling the assertion of the WDOG_B external timeout signal
74 When running this way, the need to reset the system due to watchdog
75 timeout is signaled by driving the WDOG_B line low; some external
79 driver attempts to backstop this external reset by scheduling an
81 The interrupt handler waits 1 second for the external reset to occur,
82 then it triggers a normal software reset.
84 pins on the chip.
86 .Va fsl,external-reset
93 .Va timeout-secs
95 using the given timeout value.