Lines Matching +full:external +full:- +full:signal

36 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
53 0.5 to 128 seconds, in half-second increments.
55 timeout period can be changed to any valid non-zero value.
57 At power-on, a special 16-second
58 .Sq power-down timer
60 It will assert the external WDOG_B signal, which may be connected to
61 external hardware that causes the system to reset or power-down.
62 The power-down timer is often reset by the boot loader (typically U-Boot).
63 If the power-down timer is still active at the time when the normal
71 .Va fsl,external-reset
72 property by enabling the assertion of the WDOG_B external timeout signal
75 timeout is signaled by driving the WDOG_B line low; some external
79 driver attempts to backstop this external reset by scheduling an
81 The interrupt handler waits 1 second for the external reset to occur,
83 Note that the WDOG_B signal can be configured to use a variety of
86 .Va fsl,external-reset
87 property to be effective, the signal must be connected to an appropriate
93 .Va timeout-secs