Lines Matching +full:device +full:- +full:level

30 .Nd Zynq PL device config interface
32 .Cd device devcfg
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
38 On the first write to the character device at file offset 0, the
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
44 When the PL asserts the DONE signal, the devcfg driver will enable the level
45 shifters and release the top-level PL reset signals.
48 device like this:
49 .Bd -literal -offset indent
59 .Bd -literal -offset indent
60 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
68 .Bl -tag -width 4n
75 This variable controls if the PS-PL level shifters are enabled after the
80 Changing this value has no effect on the level shifters until the next device
84 .Bl -tag -width 12n
86 Character device for the
91 Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)