Lines Matching full:pl
30 .Nd Zynq PL device config interface
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
42 and clears the PL configuration.
44 When the PL asserts the DONE signal, the devcfg driver will enable the level
45 shifters and release the top-level PL reset signals.
47 The PL (FPGA) can be configured by writing the bitstream to the character
71 This variable always reflects the status of the PL's DONE signal.
72 A 1 means the PL section has been properly programmed.
75 This variable controls if the PS-PL level shifters are enabled after the
77 This variable is 1 by default but setting it to 0 allows the PL section to be