Lines Matching +full:i2c +full:- +full:scl +full:- +full:hz

30 .Nd I2C bus system
41 system provides a uniform, modular and architecture-independent
42 system for the implementation of drivers to control various I2C devices
43 and to utilize different I2C controllers.
44 .Sh I2C
45 I2C is an acronym for Inter Integrated Circuit bus.
46 The I2C bus was developed
49 easy way to connect a CPU to peripheral chips in a TV-set.
52 The active wires, SDA and SCL, are both bidirectional.
54 Serial DAta line and SCL is the Serial CLock line.
66 In the I2C protocol
71 As mentioned before, the IC bus is a Multi-MASTER BUS.
75 Some I2C device drivers are available:
77 .Bl -column "Device drivers" -compact
81 .It Sy iicsmb Ta "I2C to SMB software bridge"
84 The I2C protocol may be implemented by hardware or software.
89 8-bit characters they write to the bus according to the I2C protocol.
91 I2C interfaces may act on the bus as slave devices, allowing spontaneous
92 bidirectional communications, thanks to the multi-master capabilities of the
93 I2C protocol.
95 Some I2C interfaces are available:
97 .Bl -column "Interface drivers" -compact
100 .It Sy iicbb Ta "generic bit-banging master-only driver"
101 .It Sy lpbb Ta "parallel port specific bit-banging interface"
104 The operating frequency of an I2C bus may be fixed or configurable.
109 A general purpose I2C bus, such as those found in many embedded systems,
112 When a system supports multiple I2C buses, a different frequency can
127 to the frequency in Hz, on systems that use device hints to configure
128 I2C devices.
132 Configure the I2C bus speed using the FDT standard
133 .Va clock-frequency
134 property of the node describing the I2C controller hardware.
143 .Xr i2c 8
154 .Xr i2c 8