Lines Matching +full:single +full:- +full:cpu

35 .Bd -ragged -offset indent
41 .Bl -ohang
57 .Bd -literal
63 controls how much per-CPU event timers should driver attempt to register.
72 This hardware includes single main counter with known increment frequency
81 Interrupt can be either edge- or level-triggered.
84 If it is not possible, it uses single sharable IRQ from PCI range.
88 Event timers provided by the driver support both one-shot an periodic modes
89 and irrelevant to CPU power states.
92 comparator as separate event timer or group them into one or several per-CPU
95 group is bound to specific CPU core.