Lines Matching +full:pci +full:- +full:to +full:- +full:cpu

14 .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 .Bd -ragged -offset indent
41 .Bl -ohang
44 Each set bit allows driver to use respective IRQ,
50 Setting to 0, disables it.
57 .Bd -literal
63 controls how much per-CPU event timers should driver attempt to register.
64 This functionality requires every comparator in a group to have own unshared
70 usually enumerated via ACPI) to supply kernel with one time counter and
71 several (usually from 3 to 8) event timers.
78 delivered as regular I/O APIC interrupt (ISA or PCI) in range from 0 to 31,
79 or as Front Side Bus interrupt, alike to PCI MSI interrupts, or in so called
81 Interrupt can be either edge- or level-triggered.
82 In last case they could be safely shared with PCI IRQs.
83 Driver prefers to use FSB interrupts, if supported, to avoid sharing.
84 If it is not possible, it uses single sharable IRQ from PCI range.
85 Other modes (LegacyReplacement and ISA IRQs) require special care to setup,
88 Event timers provided by the driver support both one-shot an periodic modes
89 and irrelevant to CPU power states.
92 comparator as separate event timer or group them into one or several per-CPU
95 group is bound to specific CPU core.