Lines Matching +full:isa +full:- +full:extensions

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58 .TH OPENSSL_RISCVCAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_riscvcap \- the RISC\-V processor capabilities vector
72 libcrypto supports RISC-V instruction set extensions. These
73 extensions are denoted by individual extension names in the capabilities
75 returned by the RISC-V Hardware Probing syscall (hwprobe) are stored
82 The environment variable is similar to the RISC-V ISA string defined in the
83 RISC-V Instruction Set Manual. It is case insensitive. Though due to the limit
96 Currently only these extensions are recognized:
104 Basic bit-manipulation
109 Carry-less multiplication
114 Single-bit instructions
119 Bit-manipulation for Cryptography
124 Carry-less multiplication for Cryptography
172 Vector Basic Bit-manipulation
182 Vector Cryptography Bit-manipulation
197 NIST Suite: Vector SHA\-2 Secure Hash
202 NIST Suite: Vector SHA\-2 Secure Hash
223 \& $ openssl info \-cpusettings
227 Disables all instruction set extensions: