Lines Matching +full:4 +full:- +full:7
5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
28 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
39 "Counter": "0,1,2,3,4,5,6,7",
43 "PEBScounters": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
55 "PEBScounters": "0,1,2,3,4,5,6,7",
63 "Counter": "0,1,2,3,4,5,6,7",
67 "PEBScounters": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
79 "PEBScounters": "0,1,2,3,4,5,6,7",
87 "Counter": "0,1,2,3,4,5,6,7",
91 "PEBScounters": "0,1,2,3,4,5,6,7",
99 "Counter": "0,1,2,3,4,5,6,7",
103 "PEBScounters": "0,1,2,3,4,5,6,7",
111 "Counter": "0,1,2,3,4,5,6,7",
115 "PEBScounters": "0,1,2,3,4,5,6,7",
123 "Counter": "0,1,2,3,4,5,6,7",
127 "PEBScounters": "0,1,2,3,4,5,6,7",
135 "Counter": "0,1,2,3,4,5,6,7",
139 "PEBScounters": "0,1,2,3,4,5,6,7",
146 "Counter": "0,1,2,3,4,5,6,7",
150 "PEBScounters": "0,1,2,3,4,5,6,7",
156 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
158 "Counter": "0,1,2,3,4,5,6,7",
162 "PEBScounters": "0,1,2,3,4,5,6,7",
170 "Counter": "0,1,2,3,4,5,6,7",
174 "PEBScounters": "0,1,2,3,4,5,6,7",
180 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
182 "Counter": "0,1,2,3,4,5,6,7",
186 "PEBScounters": "0,1,2,3,4,5,6,7",
187 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
194 "Counter": "0,1,2,3,4,5,6,7",
198 "PEBScounters": "0,1,2,3,4,5,6,7",
206 "Counter": "0,1,2,3,4,5,6,7",
210 "PEBScounters": "0,1,2,3,4,5,6,7",
218 "Counter": "0,1,2,3,4,5,6,7",
221 "PEBScounters": "0,1,2,3,4,5,6,7",
229 "Counter": "0,1,2,3,4,5,6,7",
232 "PEBScounters": "0,1,2,3,4,5,6,7",
240 "Counter": "0,1,2,3,4,5,6,7",
243 "PEBScounters": "0,1,2,3,4,5,6,7",
244 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
261 "Counter": "0,1,2,3,4,5,6,7",
264 "PEBScounters": "0,1,2,3,4,5,6,7",
282 "Counter": "0,1,2,3,4,5,6,7",
285 "PEBScounters": "0,1,2,3,4,5,6,7",
314 "Counter": "0,1,2,3,4,5,6,7",
318 "PEBScounters": "0,1,2,3,4,5,6,7",
347 "Counter": "0,1,2,3,4,5,6,7",
351 "PEBScounters": "0,1,2,3,4,5,6,7",
358 "Counter": "0,1,2,3,4,5,6,7",
359 "CounterMask": "4",
362 "PEBScounters": "0,1,2,3,4,5,6,7",
369 "Counter": "0,1,2,3,4,5,6,7",
372 "PEBScounters": "0,1,2,3,4,5,6,7",
380 "Counter": "0,1,2,3,4,5,6,7",
383 "PEBScounters": "0,1,2,3,4,5,6,7",
391 "Counter": "0,1,2,3,4,5,6,7",
394 "PEBScounters": "0,1,2,3,4,5,6,7",
400 …"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was …
402 "Counter": "0,1,2,3,4,5,6,7",
404 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
405 "PEBScounters": "0,1,2,3,4,5,6,7",
406 …"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS…
411 …": "Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle…
413 "Counter": "0,1,2,3,4,5,6,7",
417 "PEBScounters": "0,1,2,3,4,5,6,7",
418 …nts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle…
425 "Counter": "0,1,2,3,4,5,6,7",
429 "PEBScounters": "0,1,2,3,4,5,6,7",
437 "Counter": "0,1,2,3,4,5,6,7",
440 "PEBScounters": "0,1,2,3,4,5,6,7",
452 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
468 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
474 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
479 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
481 "Counter": "0,1,2,3,4,5,6,7",
485 "PEBScounters": "0,1,2,3,4,5,6,7",
486 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
492 "Counter": "0,1,2,3,4,5,6,7",
496 "PEBScounters": "0,1,2,3,4,5,6,7",
512 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
514 "Counter": "0,1,2,3,4,5,6,7",
518 "PEBScounters": "0,1,2,3,4,5,6,7",
519 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
526 "Counter": "0,1,2,3,4,5,6,7",
529 "PEBScounters": "0,1,2,3,4,5,6,7",
537 "Counter": "0,1,2,3,4,5,6,7",
540 "PEBScounters": "0,1,2,3,4,5,6,7",
548 "Counter": "0,1,2,3,4,5,6,7",
551 "PEBScounters": "0,1,2,3,4,5,6,7",
552 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
596 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
608 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
620 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
631 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
638 "Counter": "0,1,2,3,4,5,6,7",
643 "PEBScounters": "0,1,2,3,4,5,6,7",
649 "BriefDescription": "Self-modifying code (SMC) detected.",
651 "Counter": "0,1,2,3,4,5,6,7",
654 "PEBScounters": "0,1,2,3,4,5,6,7",
655 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
662 "Counter": "0,1,2,3,4,5,6,7",
665 "PEBScounters": "0,1,2,3,4,5,6,7",
672 "Counter": "0,1,2,3,4,5,6,7",
682 "Counter": "0,1,2,3,4,5,6,7",
685 "PEBScounters": "0,1,2,3,4,5,6,7",
686 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
693 "Counter": "0,1,2,3,4,5,6,7",
696 "PEBScounters": "0,1,2,3,4,5,6,7",
703 "Counter": "0,1,2,3,4,5,6,7",
706 "PEBScounters": "0,1,2,3,4,5,6,7",
707 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
714 "Counter": "0,1,2,3,4,5,6,7",
720 "PEBScounters": "0,1,2,3,4,5,6,7",
721 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
726 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
728 "Counter": "0,1,2,3,4,5,6,7",
731 "PEBScounters": "0,1,2,3,4,5,6,7",
732 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
739 "Counter": "0,1,2,3,4,5,6,7",
742 "PEBScounters": "0,1,2,3,4,5,6,7",
743 …t were issued but not retired from the specualtive path as well as the out-of-order engine recover…
748 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
753 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
758 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
760 "Counter": "0,1,2,3,4,5,6,7",
763 "PEBScounters": "0,1,2,3,4,5,6,7",
764 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
782 "Counter": "0,1,2,3,4,5,6,7",
785 "PEBScounters": "0,1,2,3,4,5,6,7",
786 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
793 "Counter": "0,1,2,3,4,5,6,7",
796 "PEBScounters": "0,1,2,3,4,5,6,7",
797 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
804 "Counter": "0,1,2,3,4,5,6,7",
807 "PEBScounters": "0,1,2,3,4,5,6,7",
808 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
813 "BriefDescription": "Number of uops executed on port 4 and 9",
815 "Counter": "0,1,2,3,4,5,6,7",
818 "PEBScounters": "0,1,2,3,4,5,6,7",
819 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
826 "Counter": "0,1,2,3,4,5,6,7",
829 "PEBScounters": "0,1,2,3,4,5,6,7",
830 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
837 "Counter": "0,1,2,3,4,5,6,7",
840 "PEBScounters": "0,1,2,3,4,5,6,7",
841 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
846 "BriefDescription": "Number of uops executed on port 7 and 8",
848 "Counter": "0,1,2,3,4,5,6,7",
851 "PEBScounters": "0,1,2,3,4,5,6,7",
852 …: "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Re…
859 "Counter": "0,1,2,3,4,5,6,7",
862 "PEBScounters": "0,1,2,3,4,5,6,7",
868 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
870 "Counter": "0,1,2,3,4,5,6,7",
874 "PEBScounters": "0,1,2,3,4,5,6,7",
875 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
880 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
882 "Counter": "0,1,2,3,4,5,6,7",
886 "PEBScounters": "0,1,2,3,4,5,6,7",
887 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
892 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
894 "Counter": "0,1,2,3,4,5,6,7",
898 "PEBScounters": "0,1,2,3,4,5,6,7",
899 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
904 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
906 "Counter": "0,1,2,3,4,5,6,7",
907 "CounterMask": "4",
910 "PEBScounters": "0,1,2,3,4,5,6,7",
911 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
916 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
918 "Counter": "0,1,2,3,4,5,6,7",
922 "PEBScounters": "0,1,2,3,4,5,6,7",
923 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
928 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
930 "Counter": "0,1,2,3,4,5,6,7",
934 "PEBScounters": "0,1,2,3,4,5,6,7",
935 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
940 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
942 "Counter": "0,1,2,3,4,5,6,7",
946 "PEBScounters": "0,1,2,3,4,5,6,7",
947 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
952 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
954 "Counter": "0,1,2,3,4,5,6,7",
955 "CounterMask": "4",
958 "PEBScounters": "0,1,2,3,4,5,6,7",
959 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
966 "Counter": "0,1,2,3,4,5,6,7",
971 "PEBScounters": "0,1,2,3,4,5,6,7",
977 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
979 "Counter": "0,1,2,3,4,5,6,7",
982 "PEBScounters": "0,1,2,3,4,5,6,7",
989 "Counter": "0,1,2,3,4,5,6,7",
992 "PEBScounters": "0,1,2,3,4,5,6,7",
1000 "Counter": "0,1,2,3,4,5,6,7",
1003 "PEBScounters": "0,1,2,3,4,5,6,7",
1011 "Counter": "0,1,2,3,4,5,6,7",
1016 "PEBScounters": "0,1,2,3,4,5,6,7",
1022 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
1024 "Counter": "0,1,2,3,4,5,6,7",
1027 "PEBScounters": "0,1,2,3,4,5,6,7",
1028 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
1035 "Counter": "0,1,2,3,4,5,6,7",
1038 "PEBScounters": "0,1,2,3,4,5,6,7",
1046 "Counter": "0,1,2,3,4,5,6,7",
1051 "PEBScounters": "0,1,2,3,4,5,6,7",
1059 "Counter": "0,1,2,3,4,5,6,7",
1064 "PEBScounters": "0,1,2,3,4,5,6,7",