Lines Matching +full:per +full:- +full:cpu
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
10 …nd undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4…
21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
24 …ue to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY …
28 …-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work…
33 …"MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.A…
36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
39 …ting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
40 … - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.…
43 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
50 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
53 … that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
57 …-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no r…
61 …BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_…
67 …BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_…
73 …- (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC…
79 …- (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O…
84 … "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
85 …- (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC…
90 … "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
91 …- (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O…
96 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
97 …- (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC…
102 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
103 …- (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.O…
108 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
109 …IRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT…
114 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
115 …IRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT…
120 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
121 ….IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_S…
126 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
127 ….IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_S…
133 …- (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MIS…
139 …- (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * …
144 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
150 "BriefDescription": "Uops Per Instruction",
156 "BriefDescription": "Instruction per taken branch",
162 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
168 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
174 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
180 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
186 "BriefDescription": "The ratio of Executed- by Issued-Uops",
190 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
193 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
199 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
205 "BriefDescription": "Floating Point Operations Per Cycle",
211 "BriefDescription": "Floating Point Operations Per Cycle",
217 …"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of th…
221 …ion": "Actual per-core usage of the Floating Point execution units (regardless of the vector width…
224 …per-core usage of the Floating Point execution units (regardless of the vector width). SMT version…
228 …per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 …
231 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
237 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
238 …BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_…
243 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
244 …BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_…
249 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
261 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
267 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
273 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
279 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
285 "BriefDescription": "Instruction per taken branch",
291 "BriefDescription": "Branch instructions per taken branch. ",
297 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
303 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
307 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
310 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
314 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
317 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
321 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
324 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
328 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
331 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
335 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
338 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
342 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
351 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
352 "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
363 …"BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instructi…
364 …- (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.…
369 …"BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instructi…
370 …- (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * …
375 "BriefDescription": "Number of Instructions per non-speculative DSB miss",
381 "BriefDescription": "Fraction of branches that are non-taken conditionals",
388 …"MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) / BR_INST_RETIRED.ALL_…
400 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_T…
405 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in co…
409 … Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overesti…
412 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
430 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
436 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
442 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
448 …"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including spe…
454 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
460 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
466 …"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including specula…
472 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
473 "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY",
478 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
484 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
490 … "BriefDescription": "Fill Buffer (FB) true hits per kilo instructions for retired demand loads",
509 …"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evi…
515 "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
521 "BriefDescription": "Average CPU Utilization",
533 "BriefDescription": "Giga Floating Point Operations Per Second",
545 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for ba…
549 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX…
552 … was running with power-delivery for baseline license level 0. SMT version; use when SMT is enable…
556 …-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-cu…
559 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
563 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct…
566 … core was running with power-delivery for license level 1. SMT version; use when SMT is enabled an…
570 …-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low…
573 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
577 …e the core was running with power-delivery for license level 2 (introduced in SKX). This includes…
580 …running with power-delivery for license level 2 (introduced in SKX). SMT version; use when SMT is …
584 …-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instruc…
588 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #…
599 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
623 …o external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
647 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
653 "BriefDescription": "C3 residency percent per core",
654 "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
659 "BriefDescription": "C6 residency percent per core",
660 "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
665 "BriefDescription": "C7 residency percent per core",
666 "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
671 "BriefDescription": "C2 residency percent per package",
672 "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
677 "BriefDescription": "C3 residency percent per package",
678 "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
683 "BriefDescription": "C6 residency percent per package",
684 "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
689 "BriefDescription": "C7 residency percent per package",
690 "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",