Lines Matching +full:light +full:- +full:weight

35 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
214         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
238 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
245 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
281 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
286 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
292 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
297 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
303 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
367 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
557         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
563 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
568         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
575 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
599         "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
670 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
695         "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
701 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
706         "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
712 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
796 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
808 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
820 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
831 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
849         "BriefDescription": "Self-modifying code (SMC) detected.",
855 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
887 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
902 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
908 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
917 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
926 …specualtive operations that were issued but not retired as well as the out-of-order engine recover…
941 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
946 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
951 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
957 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
1060 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1067 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1072 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1079 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1084 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1091 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1096 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1103 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1108         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1115         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1120         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1127         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1132         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1139         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1144         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1151         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1181         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",