42         "BriefDescription": "Speculative and retired macro-conditional branches.",
51 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
87         "BriefDescription": "Not taken macro-conditional branches.",
96         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
105 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
158         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
168         "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
187 … "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
197 …t and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
207         "BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
217         "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
334 …     "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
340 …     "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
345 …"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).…
355 …ption": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
365 …  "BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
375 …     "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
486 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
496 …"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-com…
516 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
526 …scription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this th…
558 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
563 …    "BriefDescription": "Number of instructions retired. General Counter   - architectural event.",
571         "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
623 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
650 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
655 …store.  See the table of not supported store forwards in the Intel 64 and IA-32 Architectures Opti…
679 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
688 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
742 …"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flo…
747         "BriefDescription": "Self-modifying code (SMC) detected.",
752 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
766         "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
775 …      "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
781 …cuting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mo…
800 …, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel 64 and I…
805         "BriefDescription": "Resource-related stall cycles.",
850         "BriefDescription": "Cycles stalled due to re-order buffer full.",
938         "Invert": "1",  string
1075 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1085 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1095 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1105 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1115         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1120         "Invert": "1",  string
1130 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
1142         "Invert": "1",  string
1153         "Invert": "1",  string
1158         "BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
1164         "PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)",
1175         "Invert": "1",  string
1180         "BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
1186 …- meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determini…
1197         "Invert": "1",  string
1208         "Invert": "1",  string