4         "Counter": "0,1,2,3",  string
5         "CounterHTOff": "0,1,2,3,4,5,6,7",
6         "EventCode": "0xB6",
9         "UMask": "0x1"
13         "Counter": "0,1,2,3",  string
14         "CounterHTOff": "0,1,2,3,4,5,6,7",
17         "EventCode": "0x14",
21         "UMask": "0x1"
25         "Counter": "0,1,2,3",  string
26         "CounterHTOff": "0,1,2,3,4,5,6,7",
27         "EventCode": "0x14",
30         "UMask": "0x1"
34         "Counter": "0,1,2,3",  string
35         "CounterHTOff": "0,1,2,3,4,5,6,7",
36         "EventCode": "0x88",
39         "UMask": "0xff"
42         "BriefDescription": "Speculative and retired macro-conditional branches.",
43         "Counter": "0,1,2,3",  string
44         "CounterHTOff": "0,1,2,3,4,5,6,7",
45         "EventCode": "0x88",
48         "UMask": "0xc1"
51 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
52         "Counter": "0,1,2,3",  string
53         "CounterHTOff": "0,1,2,3,4,5,6,7",
54         "EventCode": "0x88",
57         "UMask": "0xc2"
61         "Counter": "0,1,2,3",  string
62         "CounterHTOff": "0,1,2,3,4,5,6,7",
63         "EventCode": "0x88",
66         "UMask": "0xd0"
70         "Counter": "0,1,2,3",  string
71         "CounterHTOff": "0,1,2,3,4,5,6,7",
72         "EventCode": "0x88",
75         "UMask": "0xc4"
79         "Counter": "0,1,2,3",  string
80         "CounterHTOff": "0,1,2,3,4,5,6,7",
81         "EventCode": "0x88",
84         "UMask": "0xc8"
87         "BriefDescription": "Not taken macro-conditional branches.",
88         "Counter": "0,1,2,3",  string
89         "CounterHTOff": "0,1,2,3,4,5,6,7",
90         "EventCode": "0x88",
93         "UMask": "0x41"
96         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
97         "Counter": "0,1,2,3",  string
98         "CounterHTOff": "0,1,2,3,4,5,6,7",
99         "EventCode": "0x88",
102         "UMask": "0x81"
105 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
106         "Counter": "0,1,2,3",  string
107         "CounterHTOff": "0,1,2,3,4,5,6,7",
108         "EventCode": "0x88",
111         "UMask": "0x82"
115         "Counter": "0,1,2,3",  string
116         "CounterHTOff": "0,1,2,3,4,5,6,7",
117         "EventCode": "0x88",
120         "UMask": "0x90"
124         "Counter": "0,1,2,3",  string
125         "CounterHTOff": "0,1,2,3,4,5,6,7",
126         "EventCode": "0x88",
129         "UMask": "0x84"
133         "Counter": "0,1,2,3",  string
134         "CounterHTOff": "0,1,2,3,4,5,6,7",
135         "EventCode": "0x88",
138         "UMask": "0xa0"
142         "Counter": "0,1,2,3",  string
143         "CounterHTOff": "0,1,2,3,4,5,6,7",
144         "EventCode": "0x88",
147         "UMask": "0x88"
151         "Counter": "0,1,2,3",  string
152         "CounterHTOff": "0,1,2,3,4,5,6,7",
153         "EventCode": "0xC4",
158         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
159         "Counter": "0,1,2,3",  string
160         "CounterHTOff": "0,1,2,3",
161         "EventCode": "0xC4",
165         "UMask": "0x4"
169         "Counter": "0,1,2,3",  string
170         "CounterHTOff": "0,1,2,3,4,5,6,7",
171         "EventCode": "0xC4",
175         "UMask": "0x1"
179         "Counter": "0,1,2,3",  string
180         "CounterHTOff": "0,1,2,3,4,5,6,7",
181         "EventCode": "0xC4",
184         "UMask": "0x40"
188         "Counter": "0,1,2,3",  string
189         "CounterHTOff": "0,1,2,3,4,5,6,7",
190         "EventCode": "0xC4",
194         "UMask": "0x2"
198         "Counter": "0,1,2,3",  string
199         "CounterHTOff": "0,1,2,3,4,5,6,7",
200         "EventCode": "0xC4",
204         "UMask": "0x8"
208         "Counter": "0,1,2,3",  string
209         "CounterHTOff": "0,1,2,3,4,5,6,7",
210         "EventCode": "0xC4",
214         "UMask": "0x20"
218         "Counter": "0,1,2,3",  string
219         "CounterHTOff": "0,1,2,3,4,5,6,7",
220         "EventCode": "0xC4",
223         "UMask": "0x10"
227         "Counter": "0,1,2,3",  string
228         "CounterHTOff": "0,1,2,3,4,5,6,7",
229         "EventCode": "0x89",
232         "UMask": "0xff"
236         "Counter": "0,1,2,3",  string
237         "CounterHTOff": "0,1,2,3,4,5,6,7",
238         "EventCode": "0x89",
241         "UMask": "0xc1"
245         "Counter": "0,1,2,3",  string
246         "CounterHTOff": "0,1,2,3,4,5,6,7",
247         "EventCode": "0x89",
250         "UMask": "0xd0"
254         "Counter": "0,1,2,3",  string
255         "CounterHTOff": "0,1,2,3,4,5,6,7",
256         "EventCode": "0x89",
259         "UMask": "0xc4"
263         "Counter": "0,1,2,3",  string
264         "CounterHTOff": "0,1,2,3,4,5,6,7",
265         "EventCode": "0x89",
268         "UMask": "0x41"
272         "Counter": "0,1,2,3",  string
273         "CounterHTOff": "0,1,2,3,4,5,6,7",
274         "EventCode": "0x89",
277         "UMask": "0x81"
281         "Counter": "0,1,2,3",  string
282         "CounterHTOff": "0,1,2,3,4,5,6,7",
283         "EventCode": "0x89",
286         "UMask": "0x90"
290         "Counter": "0,1,2,3",  string
291         "CounterHTOff": "0,1,2,3,4,5,6,7",
292         "EventCode": "0x89",
295         "UMask": "0x84"
299         "Counter": "0,1,2,3",  string
300         "CounterHTOff": "0,1,2,3,4,5,6,7",
301         "EventCode": "0x89",
304         "UMask": "0xa0"
308         "Counter": "0,1,2,3",  string
309         "CounterHTOff": "0,1,2,3,4,5,6,7",
310         "EventCode": "0x89",
313         "UMask": "0x88"
317         "Counter": "0,1,2,3",  string
318         "CounterHTOff": "0,1,2,3,4,5,6,7",
319         "EventCode": "0xC5",
324 …     "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
325         "Counter": "0,1,2,3",  string
326         "CounterHTOff": "0,1,2,3",
327         "EventCode": "0xC5",
330 …     "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
332         "UMask": "0x4"
336         "Counter": "0,1,2,3",  string
337         "CounterHTOff": "0,1,2,3,4,5,6,7",
338         "EventCode": "0xC5",
342         "UMask": "0x1"
346         "Counter": "0,1,2,3",  string
347         "CounterHTOff": "0,1,2,3,4,5,6,7",
348         "EventCode": "0xC5",
352         "UMask": "0x2"
356         "Counter": "0,1,2,3",  string
357         "CounterHTOff": "0,1,2,3,4,5,6,7",
358         "EventCode": "0xC5",
362         "UMask": "0x10"
366         "Counter": "0,1,2,3",  string
367         "CounterHTOff": "0,1,2,3,4,5,6,7",
368         "EventCode": "0xC5",
372         "UMask": "0x20"
376         "Counter": "0,1,2,3",  string
377         "CounterHTOff": "0,1,2,3",
378         "EventCode": "0x3C",
381         "UMask": "0x2"
385         "Counter": "0,1,2,3",  string
386         "CounterHTOff": "0,1,2,3,4,5,6,7",
387         "EventCode": "0x3C",
390         "UMask": "0x1"
395         "Counter": "0,1,2,3",  string
396         "CounterHTOff": "0,1,2,3,4,5,6,7",
397         "EventCode": "0x3C",
400         "UMask": "0x1"
404         "Counter": "0,1,2,3",  string
405         "CounterHTOff": "0,1,2,3,4,5,6,7",
406         "EventCode": "0x3C",
409         "UMask": "0x2"
413         "Counter": "Fixed counter 3",  string
414         "CounterHTOff": "Fixed counter 3",
416 …counter. This event can approximate elapsed time while the core was not in a halt state. This even…
418         "UMask": "0x3"
422         "Counter": "0,1,2,3",  string
423         "CounterHTOff": "0,1,2,3,4,5,6,7",
424         "EventCode": "0x3C",
428         "UMask": "0x1"
433         "Counter": "0,1,2,3",  string
434         "CounterHTOff": "0,1,2,3,4,5,6,7",
435         "EventCode": "0x3C",
438         "UMask": "0x1"
442         "Counter": "Fixed counter 2",  string
443         "CounterHTOff": "Fixed counter 2",
445 …e the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four…
447         "UMask": "0x2"
452         "Counter": "Fixed counter 2",  string
453         "CounterHTOff": "Fixed counter 2",
456         "UMask": "0x2"
460         "Counter": "0,1,2,3",  string
461         "CounterHTOff": "0,1,2,3,4,5,6,7",
462         "EventCode": "0x3C",
469         "Counter": "0,1,2,3",  string
470         "CounterHTOff": "0,1,2,3,4,5,6,7",
471         "EventCode": "0x3C",
476 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
477         "Counter": "2",  string
480         "EventCode": "0xA3",
483         "UMask": "0x2"
486 …-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load…
487         "Counter": "0,1,2,3",  string
488         "CounterHTOff": "0,1,2,3,4,5,6,7",
490         "EventCode": "0xA3",
493         "UMask": "0x1"
497         "Counter": "0,1,2,3",  string
498         "CounterHTOff": "0,1,2,3",
500         "EventCode": "0xA3",
503         "UMask": "0x4"
506 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
507         "Counter": "2",  string
510         "EventCode": "0xA3",
513         "UMask": "0x6"
516 …-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry…
517         "Counter": "0,1,2,3",  string
518         "CounterHTOff": "0,1,2,3",
520         "EventCode": "0xA3",
523         "UMask": "0x5"
527         "Counter": "0,1,2,3",  string
528         "CounterHTOff": "0,1,2,3,4,5,6,7",
529         "EventCode": "0x87",
532         "UMask": "0x4"
536         "Counter": "0,1,2,3",  string
537         "CounterHTOff": "0,1,2,3,4,5,6,7",
538         "EventCode": "0x87",
541         "UMask": "0x1"
545         "Counter": "Fixed counter 1",  string
546         "CounterHTOff": "Fixed counter 1",
548 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
550         "UMask": "0x1"
553 …    "BriefDescription": "Number of instructions retired. General Counter   - architectural event.",
554         "Counter": "0,1,2,3",  string
555         "CounterHTOff": "0,1,2,3,4,5,6,7",
556         "EventCode": "0xC0",
561         "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
562         "Counter": "1",  string
564         "EventCode": "0xC0",
569         "UMask": "0x1"
573         "Counter": "0,1,2,3",  string
574         "CounterHTOff": "0,1,2,3,4,5,6,7",
575         "EventCode": "0x0D",
578         "UMask": "0x40"
582         "Counter": "0,1,2,3",  string
583         "CounterHTOff": "0,1,2,3,4,5,6,7",
585         "EventCode": "0x0D",
588         "UMask": "0x3"
593         "Counter": "0,1,2,3",  string
594         "CounterHTOff": "0,1,2,3,4,5,6,7",
596         "EventCode": "0x0D",
599         "UMask": "0x3"
603         "Counter": "0,1,2,3",  string
604         "CounterHTOff": "0,1,2,3,4,5,6,7",
607         "EventCode": "0x0D",
610         "UMask": "0x3"
613 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
614         "Counter": "0,1,2,3",  string
615         "CounterHTOff": "0,1,2,3,4,5,6,7",
616         "EventCode": "0x03",
619         "UMask": "0x10"
623         "Counter": "0,1,2,3",  string
624         "CounterHTOff": "0,1,2,3,4,5,6,7",
625         "EventCode": "0x03",
628         "UMask": "0x1"
632         "Counter": "0,1,2,3",  string
633         "CounterHTOff": "0,1,2,3,4,5,6,7",
634         "EventCode": "0x03",
637         "UMask": "0x8"
640 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
641         "Counter": "0,1,2,3",  string
642         "CounterHTOff": "0,1,2,3,4,5,6,7",
643         "EventCode": "0x03",
645 …tore.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Opti…
647         "UMask": "0x2"
651         "Counter": "0,1,2,3",  string
652         "CounterHTOff": "0,1,2,3,4,5,6,7",
653         "EventCode": "0x07",
657         "UMask": "0x1"
661         "Counter": "0,1,2,3",  string
662         "CounterHTOff": "0,1,2,3,4,5,6,7",
663         "EventCode": "0x07",
666         "UMask": "0x8"
669 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
670         "Counter": "0,1,2,3",  string
671         "CounterHTOff": "0,1,2,3,4,5,6,7",
672         "EventCode": "0x4C",
675         "UMask": "0x2"
678 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
679         "Counter": "0,1,2,3",  string
680         "CounterHTOff": "0,1,2,3,4,5,6,7",
681         "EventCode": "0x4C",
684         "UMask": "0x1"
688         "Counter": "0,1,2,3",  string
689         "CounterHTOff": "0,1,2,3,4,5,6,7",
691         "EventCode": "0xA8",
694         "UMask": "0x1"
698         "Counter": "0,1,2,3",  string
699         "CounterHTOff": "0,1,2,3,4,5,6,7",
701         "EventCode": "0xA8",
704         "UMask": "0x1"
708         "Counter": "0,1,2,3",  string
709         "CounterHTOff": "0,1,2,3,4,5,6,7",
710         "EventCode": "0xA8",
713         "UMask": "0x1"
717         "Counter": "0,1,2,3",  string
718         "CounterHTOff": "0,1,2,3,4,5,6,7",
721         "EventCode": "0xc3",
724         "UMask": "0x1"
727 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
728         "Counter": "0,1,2,3",  string
729         "CounterHTOff": "0,1,2,3,4,5,6,7",
730         "EventCode": "0xC3",
732 …ription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to in…
734         "UMask": "0x20"
737         "BriefDescription": "Self-modifying code (SMC) detected.",
738         "Counter": "0,1,2,3",  string
739         "CounterHTOff": "0,1,2,3,4,5,6,7",
740         "EventCode": "0xC3",
742 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
744         "UMask": "0x4"
748         "Counter": "0,1,2,3",  string
749         "CounterHTOff": "0,1,2,3,4,5,6,7",
750         "EventCode": "0xC1",
753         "UMask": "0x2"
756         "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
757         "Counter": "0,1,2,3",  string
758         "CounterHTOff": "0,1,2,3,4,5,6,7",
759         "EventCode": "0x59",
762         "UMask": "0x20"
765 …      "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
766         "Counter": "0,1,2,3",  string
767         "CounterHTOff": "0,1,2,3,4,5,6,7",
769         "EventCode": "0x59",
771 …cuting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mo…
773         "UMask": "0x20"
777         "Counter": "0,1,2,3",  string
778         "CounterHTOff": "0,1,2,3,4,5,6,7",
779         "EventCode": "0x59",
782         "UMask": "0x80"
786         "Counter": "0,1,2,3",  string
787         "CounterHTOff": "0,1,2,3,4,5,6,7",
788         "EventCode": "0x59",
790 … where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and I…
792         "UMask": "0x40"
795         "BriefDescription": "Resource-related stall cycles.",
796         "Counter": "0,1,2,3",  string
797         "CounterHTOff": "0,1,2,3,4,5,6,7",
798         "EventCode": "0xA2",
801         "UMask": "0x1"
805         "Counter": "0,1,2,3",  string
806         "CounterHTOff": "0,1,2,3,4,5,6,7",
807         "EventCode": "0xA2",
810         "UMask": "0x2"
814         "Counter": "0,1,2,3",  string
815         "CounterHTOff": "0,1,2,3,4,5,6,7",
816         "EventCode": "0xA2",
819         "UMask": "0xa"
823         "Counter": "0,1,2,3",  string
824         "CounterHTOff": "0,1,2,3,4,5,6,7",
825         "EventCode": "0xA2",
828         "UMask": "0xe"
832         "Counter": "0,1,2,3",  string
833         "CounterHTOff": "0,1,2,3,4,5,6,7",
834         "EventCode": "0xA2",
837         "UMask": "0xf0"
840         "BriefDescription": "Cycles stalled due to re-order buffer full.",
841         "Counter": "0,1,2,3",  string
842         "CounterHTOff": "0,1,2,3,4,5,6,7",
843         "EventCode": "0xA2",
846         "UMask": "0x10"
850         "Counter": "0,1,2,3",  string
851         "CounterHTOff": "0,1,2,3,4,5,6,7",
852         "EventCode": "0xA2",
855         "UMask": "0x4"
859         "Counter": "0,1,2,3",  string
860         "CounterHTOff": "0,1,2,3,4,5,6,7",
861         "EventCode": "0xA2",
864         "UMask": "0x8"
868         "Counter": "0,1,2,3",  string
869         "CounterHTOff": "0,1,2,3,4,5,6,7",
870         "EventCode": "0x5B",
873         "UMask": "0xc"
877         "Counter": "0,1,2,3",  string
878         "CounterHTOff": "0,1,2,3,4,5,6,7",
879         "EventCode": "0x5B",
882         "UMask": "0xf"
886         "Counter": "0,1,2,3",  string
887         "CounterHTOff": "0,1,2,3,4,5,6,7",
888         "EventCode": "0x5B",
891         "UMask": "0x40"
895         "Counter": "0,1,2,3",  string
896         "CounterHTOff": "0,1,2,3,4,5,6,7",
897         "EventCode": "0x5B",
900         "UMask": "0x4f"
904         "Counter": "0,1,2,3",  string
905         "CounterHTOff": "0,1,2,3,4,5,6,7",
906         "EventCode": "0xCC",
909         "UMask": "0x20"
913         "Counter": "0,1,2,3",  string
914         "CounterHTOff": "0,1,2,3,4,5,6,7",
915         "EventCode": "0x5E",
918         "UMask": "0x1"
922         "Counter": "0,1,2,3",  string
923         "CounterHTOff": "0,1,2,3,4,5,6,7",
926         "EventCode": "0x5E",
930         "UMask": "0x1"
934         "Counter": "0,1,2,3",  string
935         "CounterHTOff": "0,1,2,3,4,5,6,7",
936         "EventCode": "0xB1",
939         "UMask": "0x2"
943         "Counter": "0,1,2,3",  string
944         "CounterHTOff": "0,1,2,3,4,5,6,7",
945         "EventCode": "0xB1",
948         "UMask": "0x1"
951         "BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
952         "Counter": "0,1,2,3",  string
953         "CounterHTOff": "0,1,2,3,4,5,6,7",
954         "EventCode": "0xA1",
957         "UMask": "0x1"
961         "BriefDescription": "Cycles per core when uops are dispatched to port 0.",
962         "Counter": "0,1,2,3",  string
963         "CounterHTOff": "0,1,2,3,4,5,6,7",
964         "EventCode": "0xA1",
967         "UMask": "0x1"
971         "Counter": "0,1,2,3",  string
972         "CounterHTOff": "0,1,2,3,4,5,6,7",
973         "EventCode": "0xA1",
976         "UMask": "0x2"
981         "Counter": "0,1,2,3",  string
982         "CounterHTOff": "0,1,2,3,4,5,6,7",
983         "EventCode": "0xA1",
986         "UMask": "0x2"
990         "Counter": "0,1,2,3",  string
991         "CounterHTOff": "0,1,2,3,4,5,6,7",
992         "EventCode": "0xA1",
995         "UMask": "0xc"
1000         "Counter": "0,1,2,3",  string
1001         "CounterHTOff": "0,1,2,3,4,5,6,7",
1002         "EventCode": "0xA1",
1005         "UMask": "0xc"
1009         "Counter": "0,1,2,3",  string
1010         "CounterHTOff": "0,1,2,3,4,5,6,7",
1011         "EventCode": "0xA1",
1014         "UMask": "0x30"
1019         "Counter": "0,1,2,3",  string
1020         "CounterHTOff": "0,1,2,3,4,5,6,7",
1021         "EventCode": "0xA1",
1024         "UMask": "0x30"
1028         "Counter": "0,1,2,3",  string
1029         "CounterHTOff": "0,1,2,3,4,5,6,7",
1030         "EventCode": "0xA1",
1033         "UMask": "0x40"
1038         "Counter": "0,1,2,3",  string
1039         "CounterHTOff": "0,1,2,3,4,5,6,7",
1040         "EventCode": "0xA1",
1043         "UMask": "0x40"
1047         "Counter": "0,1,2,3",  string
1048         "CounterHTOff": "0,1,2,3,4,5,6,7",
1049         "EventCode": "0xA1",
1052         "UMask": "0x80"
1057         "Counter": "0,1,2,3",  string
1058         "CounterHTOff": "0,1,2,3,4,5,6,7",
1059         "EventCode": "0xA1",
1062         "UMask": "0x80"
1065 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1066         "Counter": "0,1,2,3",  string
1067         "CounterHTOff": "0,1,2,3,4,5,6,7",
1069         "EventCode": "0xB1",
1072         "UMask": "0x2"
1075 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1076         "Counter": "0,1,2,3",  string
1077         "CounterHTOff": "0,1,2,3,4,5,6,7",
1079         "EventCode": "0xB1",
1082         "UMask": "0x2"
1085 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1086         "Counter": "0,1,2,3",  string
1087         "CounterHTOff": "0,1,2,3,4,5,6,7",
1089         "EventCode": "0xB1",
1092         "UMask": "0x2"
1095 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1096         "Counter": "0,1,2,3",  string
1097         "CounterHTOff": "0,1,2,3,4,5,6,7",
1099         "EventCode": "0xB1",
1102         "UMask": "0x2"
1105         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1106         "Counter": "0,1,2,3",  string
1107         "CounterHTOff": "0,1,2,3,4,5,6,7",
1108         "EventCode": "0xB1",
1112         "UMask": "0x2"
1116         "Counter": "0,1,2,3",  string
1117         "CounterHTOff": "0,1,2,3,4,5,6,7",
1118         "EventCode": "0x0E",
1120 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
1122         "UMask": "0x1"
1127         "Counter": "0,1,2,3",  string
1128         "CounterHTOff": "0,1,2,3",
1130         "EventCode": "0x0E",
1134         "UMask": "0x1"
1138         "Counter": "0,1,2,3",  string
1139         "CounterHTOff": "0,1,2,3",
1141         "EventCode": "0x0E",
1145         "UMask": "0x1"
1149         "Counter": "0,1,2,3",  string
1150         "CounterHTOff": "0,1,2,3,4,5,6,7",
1151         "EventCode": "0xC2",
1154         "PublicDescription": "This event counts the number of micro-ops retired.",
1156         "UMask": "0x1"
1160         "Counter": "0,1,2,3",  string
1161         "CounterHTOff": "0,1,2,3",
1163         "EventCode": "0xC2",
1167         "UMask": "0x1"
1171         "Counter": "0,1,2,3",  string
1172         "CounterHTOff": "0,1,2,3,4,5,6,7",
1173         "EventCode": "0xC2",
1176 …h cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in d…
1178         "UMask": "0x2"
1182         "Counter": "0,1,2,3",  string
1183         "CounterHTOff": "0,1,2,3",
1185         "EventCode": "0xC2",
1189         "UMask": "0x1"
1193         "Counter": "0,1,2,3",  string
1194         "CounterHTOff": "0,1,2,3",
1196         "EventCode": "0xC2",
1200         "UMask": "0x1"