Lines Matching +full:counter +full:- +full:0
4 "Counter": "0,1,2,3", string
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 "EventCode": "0x14",
12 "UMask": "0x4"
16 "Counter": "0,1,2,3", string
17 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 "EventCode": "0x14",
22 "UMask": "0x1"
26 "Counter": "0,1,2,3", string
27 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 "EventCode": "0x88",
32 "UMask": "0xff"
35 "BriefDescription": "Speculative and retired macro-conditional branches",
36 "Counter": "0,1,2,3", string
37 "CounterHTOff": "0,1,2,3,4,5,6,7",
38 "EventCode": "0x88",
40 "PublicDescription": "Speculative and retired macro-conditional branches.",
42 "UMask": "0xc1"
45 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
46 "Counter": "0,1,2,3", string
47 "CounterHTOff": "0,1,2,3,4,5,6,7",
48 "EventCode": "0x88",
50 …"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and ind…
52 "UMask": "0xc2"
56 "Counter": "0,1,2,3", string
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
58 "EventCode": "0x88",
62 "UMask": "0xd0"
66 "Counter": "0,1,2,3", string
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
68 "EventCode": "0x88",
72 "UMask": "0xc4"
76 "Counter": "0,1,2,3", string
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
78 "EventCode": "0x88",
81 "UMask": "0xc8"
84 "BriefDescription": "Not taken macro-conditional branches",
85 "Counter": "0,1,2,3", string
86 "CounterHTOff": "0,1,2,3,4,5,6,7",
87 "EventCode": "0x88",
89 "PublicDescription": "Not taken macro-conditional branches.",
91 "UMask": "0x41"
94 "BriefDescription": "Taken speculative and retired macro-conditional branches",
95 "Counter": "0,1,2,3", string
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "EventCode": "0x88",
99 "PublicDescription": "Taken speculative and retired macro-conditional branches.",
101 "UMask": "0x81"
104 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
105 "Counter": "0,1,2,3", string
106 "CounterHTOff": "0,1,2,3,4,5,6,7",
107 "EventCode": "0x88",
109 …"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excludin…
111 "UMask": "0x82"
115 "Counter": "0,1,2,3", string
116 "CounterHTOff": "0,1,2,3,4,5,6,7",
117 "EventCode": "0x88",
121 "UMask": "0x90"
125 "Counter": "0,1,2,3", string
126 "CounterHTOff": "0,1,2,3,4,5,6,7",
127 "EventCode": "0x88",
131 "UMask": "0x84"
135 "Counter": "0,1,2,3", string
136 "CounterHTOff": "0,1,2,3,4,5,6,7",
137 "EventCode": "0x88",
141 "UMask": "0xa0"
145 "Counter": "0,1,2,3", string
146 "CounterHTOff": "0,1,2,3,4,5,6,7",
147 "EventCode": "0x88",
151 "UMask": "0x88"
155 "Counter": "0,1,2,3", string
156 "CounterHTOff": "0,1,2,3,4,5,6,7",
157 "EventCode": "0xC4",
164 "Counter": "0,1,2,3", string
165 "CounterHTOff": "0,1,2,3",
166 "EventCode": "0xC4",
170 "UMask": "0x4"
174 "Counter": "0,1,2,3", string
175 "CounterHTOff": "0,1,2,3,4,5,6,7",
176 "EventCode": "0xC4",
180 "UMask": "0x1"
184 "Counter": "0,1,2,3", string
185 "CounterHTOff": "0,1,2,3,4,5,6,7",
186 "EventCode": "0xC4",
190 "UMask": "0x40"
194 "Counter": "0,1,2,3", string
195 "CounterHTOff": "0,1,2,3,4,5,6,7",
196 "EventCode": "0xC4",
200 "UMask": "0x2"
204 "Counter": "0,1,2,3", string
205 "CounterHTOff": "0,1,2,3,4,5,6,7",
206 "EventCode": "0xC4",
210 "UMask": "0x2"
214 "Counter": "0,1,2,3", string
215 "CounterHTOff": "0,1,2,3,4,5,6,7",
216 "EventCode": "0xC4",
220 "UMask": "0x8"
224 "Counter": "0,1,2,3", string
225 "CounterHTOff": "0,1,2,3,4,5,6,7",
226 "EventCode": "0xC4",
230 "UMask": "0x20"
234 "Counter": "0,1,2,3", string
235 "CounterHTOff": "0,1,2,3,4,5,6,7",
236 "EventCode": "0xC4",
240 "UMask": "0x10"
244 "Counter": "0,1,2,3", string
245 "CounterHTOff": "0,1,2,3,4,5,6,7",
246 "EventCode": "0x89",
250 "UMask": "0xff"
254 "Counter": "0,1,2,3", string
255 "CounterHTOff": "0,1,2,3,4,5,6,7",
256 "EventCode": "0x89",
260 "UMask": "0xc1"
264 "Counter": "0,1,2,3", string
265 "CounterHTOff": "0,1,2,3,4,5,6,7",
266 "EventCode": "0x89",
270 "UMask": "0xc4"
274 "Counter": "0,1,2,3", string
275 "CounterHTOff": "0,1,2,3,4,5,6,7",
276 "EventCode": "0x89",
280 "UMask": "0x41"
284 "Counter": "0,1,2,3", string
285 "CounterHTOff": "0,1,2,3,4,5,6,7",
286 "EventCode": "0x89",
290 "UMask": "0x81"
294 "Counter": "0,1,2,3", string
295 "CounterHTOff": "0,1,2,3,4,5,6,7",
296 "EventCode": "0x89",
300 "UMask": "0x84"
304 "Counter": "0,1,2,3", string
305 "CounterHTOff": "0,1,2,3,4,5,6,7",
306 "EventCode": "0x89",
310 "UMask": "0xa0"
314 "Counter": "0,1,2,3", string
315 "CounterHTOff": "0,1,2,3,4,5,6,7",
316 "EventCode": "0x89",
320 "UMask": "0x88"
324 "Counter": "0,1,2,3", string
325 "CounterHTOff": "0,1,2,3,4,5,6,7",
326 "EventCode": "0xC5",
333 "Counter": "0,1,2,3", string
334 "CounterHTOff": "0,1,2,3",
335 "EventCode": "0xC5",
339 "UMask": "0x4"
343 "Counter": "0,1,2,3", string
344 "CounterHTOff": "0,1,2,3,4,5,6,7",
345 "EventCode": "0xC5",
349 "UMask": "0x1"
353 "Counter": "0,1,2,3", string
354 "CounterHTOff": "0,1,2,3,4,5,6,7",
355 "EventCode": "0xC5",
359 "UMask": "0x20"
363 "Counter": "0,1,2,3", string
364 "CounterHTOff": "0,1,2,3",
365 "EventCode": "0x3C",
368 "UMask": "0x2"
372 "Counter": "0,1,2,3", string
373 "CounterHTOff": "0,1,2,3,4,5,6,7",
374 "EventCode": "0x3C",
378 "UMask": "0x1"
383 "Counter": "0,1,2,3", string
384 "CounterHTOff": "0,1,2,3,4,5,6,7",
385 "EventCode": "0x3C",
388 "UMask": "0x1"
392 "Counter": "0,1,2,3", string
393 "CounterHTOff": "0,1,2,3,4,5,6,7",
394 "EventCode": "0x3C",
397 "UMask": "0x2"
401 "Counter": "Fixed counter 2", string
402 "CounterHTOff": "Fixed counter 2",
405 "UMask": "0x3"
409 "Counter": "0,1,2,3", string
410 "CounterHTOff": "0,1,2,3,4,5,6,7",
411 "EventCode": "0x3C",
415 "UMask": "0x1"
420 "Counter": "0,1,2,3", string
421 "CounterHTOff": "0,1,2,3,4,5,6,7",
422 "EventCode": "0x3C",
425 "UMask": "0x1"
429 "Counter": "Fixed counter 1", string
430 "CounterHTOff": "Fixed counter 1",
433 "UMask": "0x2"
438 "Counter": "Fixed counter 1", string
439 "CounterHTOff": "Fixed counter 1",
443 "UMask": "0x2"
447 "Counter": "0,1,2,3", string
448 "CounterHTOff": "0,1,2,3,4,5,6,7",
449 "EventCode": "0x3C",
457 "Counter": "0,1,2,3", string
458 "CounterHTOff": "0,1,2,3,4,5,6,7",
459 "EventCode": "0x3C",
466 "Counter": "2", string
469 "EventCode": "0xA3",
472 "UMask": "0x8"
476 "Counter": "2", string
479 "EventCode": "0xA3",
483 "UMask": "0x8"
487 "Counter": "0,1,2,3", string
488 "CounterHTOff": "0,1,2,3,4,5,6,7",
490 "EventCode": "0xA3",
493 "UMask": "0x1"
497 "Counter": "0,1,2,3", string
498 "CounterHTOff": "0,1,2,3,4,5,6,7",
500 "EventCode": "0xA3",
504 "UMask": "0x1"
508 "Counter": "0,1,2,3", string
509 "CounterHTOff": "0,1,2,3",
511 "EventCode": "0xA3",
515 "UMask": "0x2"
519 "Counter": "0,1,2,3", string
520 "CounterHTOff": "0,1,2,3",
522 "EventCode": "0xA3",
525 "UMask": "0x2"
529 "Counter": "0,1,2,3", string
530 "CounterHTOff": "0,1,2,3",
532 "EventCode": "0xA3",
536 "UMask": "0x4"
540 "Counter": "2", string
543 "EventCode": "0xA3",
546 "UMask": "0xc"
550 "Counter": "2", string
553 "EventCode": "0xA3",
555 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.",
557 "UMask": "0xc"
561 "Counter": "0,1,2,3", string
562 "CounterHTOff": "0,1,2,3",
564 "EventCode": "0xA3",
567 "UMask": "0x5"
571 "Counter": "0,1,2,3", string
572 "CounterHTOff": "0,1,2,3",
574 "EventCode": "0xA3",
578 "UMask": "0x5"
582 "Counter": "0,1,2,3", string
583 "CounterHTOff": "0,1,2,3",
585 "EventCode": "0xA3",
588 "UMask": "0x6"
592 "Counter": "0,1,2,3", string
593 "CounterHTOff": "0,1,2,3",
595 "EventCode": "0xA3",
598 "UMask": "0x6"
602 "Counter": "0,1,2,3", string
603 "CounterHTOff": "0,1,2,3",
605 "EventCode": "0xA3",
608 "UMask": "0x4"
612 "Counter": "0,1,2,3", string
613 "CounterHTOff": "0,1,2,3,4,5,6,7",
614 "EventCode": "0x87",
618 "UMask": "0x4"
622 "Counter": "0,1,2,3", string
623 "CounterHTOff": "0,1,2,3,4,5,6,7",
624 "EventCode": "0x87",
627 "UMask": "0x1"
631 "Counter": "Fixed counter 0", string
632 "CounterHTOff": "Fixed counter 0",
635 "UMask": "0x1"
638 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
639 "Counter": "0,1,2,3", string
640 "CounterHTOff": "0,1,2,3,4,5,6,7",
641 "EventCode": "0xC0",
648 "Counter": "1", string
650 "EventCode": "0xC0",
655 "UMask": "0x1"
659 "Counter": "0,1,2,3", string
660 "CounterHTOff": "0,1,2,3,4,5,6,7",
662 "EventCode": "0x0D",
665 "UMask": "0x3"
670 "Counter": "0,1,2,3", string
671 "CounterHTOff": "0,1,2,3,4,5,6,7",
673 "EventCode": "0x0D",
676 "UMask": "0x3"
680 "Counter": "0,1,2,3", string
681 "CounterHTOff": "0,1,2,3,4,5,6,7",
684 "EventCode": "0x0D",
687 "UMask": "0x3"
691 "Counter": "0,1,2,3", string
692 "CounterHTOff": "0,1,2,3,4,5,6,7",
693 "EventCode": "0x03",
697 "UMask": "0x8"
700 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
701 "Counter": "0,1,2,3", string
702 "CounterHTOff": "0,1,2,3,4,5,6,7",
703 "EventCode": "0x03",
707 "UMask": "0x2"
711 "Counter": "0,1,2,3", string
712 "CounterHTOff": "0,1,2,3,4,5,6,7",
713 "EventCode": "0x07",
717 "UMask": "0x1"
720 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
721 "Counter": "0,1,2,3", string
722 "CounterHTOff": "0,1,2,3,4,5,6,7",
723 "EventCode": "0x4C",
725 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
727 "UMask": "0x2"
730 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
731 "Counter": "0,1,2,3", string
732 "CounterHTOff": "0,1,2,3,4,5,6,7",
733 "EventCode": "0x4C",
735 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
737 "UMask": "0x1"
741 "Counter": "0,1,2,3", string
742 "CounterHTOff": "0,1,2,3,4,5,6,7",
744 "EventCode": "0xA8",
748 "UMask": "0x1"
752 "Counter": "0,1,2,3", string
753 "CounterHTOff": "0,1,2,3,4,5,6,7",
755 "EventCode": "0xA8",
759 "UMask": "0x1"
763 "Counter": "0,1,2,3", string
764 "CounterHTOff": "0,1,2,3,4,5,6,7",
765 "EventCode": "0xA8",
768 "UMask": "0x1"
772 "Counter": "0,1,2,3", string
773 "CounterHTOff": "0,1,2,3,4,5,6,7",
776 "EventCode": "0xC3",
779 "UMask": "0x1"
782 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
783 "Counter": "0,1,2,3", string
784 "CounterHTOff": "0,1,2,3,4,5,6,7",
785 "EventCode": "0xC3",
787 …ed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
789 "UMask": "0x20"
792 "BriefDescription": "Self-modifying code (SMC) detected.",
793 "Counter": "0,1,2,3", string
794 "CounterHTOff": "0,1,2,3,4,5,6,7",
795 "EventCode": "0xC3",
797 "PublicDescription": "Number of self-modifying-code machine clears detected.",
799 "UMask": "0x4"
803 "Counter": "0,1,2,3", string
804 "CounterHTOff": "0,1,2,3,4,5,6,7",
805 "EventCode": "0x58",
808 "UMask": "0x1"
812 "Counter": "0,1,2,3", string
813 "CounterHTOff": "0,1,2,3,4,5,6,7",
814 "EventCode": "0x58",
817 "UMask": "0x4"
821 "Counter": "0,1,2,3", string
822 "CounterHTOff": "0,1,2,3,4,5,6,7",
823 "EventCode": "0xC1",
826 "UMask": "0x80"
829 "BriefDescription": "Resource-related stall cycles",
830 "Counter": "0,1,2,3", string
831 "CounterHTOff": "0,1,2,3,4,5,6,7",
832 "EventCode": "0xA2",
836 "UMask": "0x1"
839 "BriefDescription": "Cycles stalled due to re-order buffer full.",
840 "Counter": "0,1,2,3", string
841 "CounterHTOff": "0,1,2,3,4,5,6,7",
842 "EventCode": "0xA2",
845 "UMask": "0x10"
849 "Counter": "0,1,2,3", string
850 "CounterHTOff": "0,1,2,3,4,5,6,7",
851 "EventCode": "0xA2",
854 "UMask": "0x4"
858 "Counter": "0,1,2,3", string
859 "CounterHTOff": "0,1,2,3,4,5,6,7",
860 "EventCode": "0xA2",
864 "UMask": "0x8"
868 "Counter": "0,1,2,3", string
869 "CounterHTOff": "0,1,2,3,4,5,6,7",
870 "EventCode": "0xCC",
874 "UMask": "0x20"
878 "Counter": "0,1,2,3", string
879 "CounterHTOff": "0,1,2,3,4,5,6,7",
880 "EventCode": "0x5E",
884 "UMask": "0x1"
888 "Counter": "0,1,2,3", string
889 "CounterHTOff": "0,1,2,3,4,5,6,7",
892 "EventCode": "0x5E",
896 "UMask": "0x1"
899 "BriefDescription": "Cycles per thread when uops are dispatched to port 0",
900 "Counter": "0,1,2,3", string
901 "CounterHTOff": "0,1,2,3,4,5,6,7",
902 "EventCode": "0xA1",
904 "PublicDescription": "Cycles which a Uop is dispatched on port 0.",
906 "UMask": "0x1"
910 "BriefDescription": "Cycles per core when uops are dispatched to port 0",
911 "Counter": "0,1,2,3", string
912 "CounterHTOff": "0,1,2,3,4,5,6,7",
913 "EventCode": "0xA1",
915 "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
917 "UMask": "0x1"
921 "Counter": "0,1,2,3", string
922 "CounterHTOff": "0,1,2,3,4,5,6,7",
923 "EventCode": "0xA1",
927 "UMask": "0x2"
932 "Counter": "0,1,2,3", string
933 "CounterHTOff": "0,1,2,3,4,5,6,7",
934 "EventCode": "0xA1",
938 "UMask": "0x2"
942 "Counter": "0,1,2,3", string
943 "CounterHTOff": "0,1,2,3,4,5,6,7",
944 "EventCode": "0xA1",
948 "UMask": "0xc"
953 "Counter": "0,1,2,3", string
954 "CounterHTOff": "0,1,2,3,4,5,6,7",
955 "EventCode": "0xA1",
958 "UMask": "0xc"
962 "Counter": "0,1,2,3", string
963 "CounterHTOff": "0,1,2,3,4,5,6,7",
964 "EventCode": "0xA1",
968 "UMask": "0x30"
973 "Counter": "0,1,2,3", string
974 "CounterHTOff": "0,1,2,3,4,5,6,7",
975 "EventCode": "0xA1",
979 "UMask": "0x30"
983 "Counter": "0,1,2,3", string
984 "CounterHTOff": "0,1,2,3,4,5,6,7",
985 "EventCode": "0xA1",
989 "UMask": "0x40"
994 "Counter": "0,1,2,3", string
995 "CounterHTOff": "0,1,2,3,4,5,6,7",
996 "EventCode": "0xA1",
1000 "UMask": "0x40"
1004 "Counter": "0,1,2,3", string
1005 "CounterHTOff": "0,1,2,3,4,5,6,7",
1006 "EventCode": "0xA1",
1010 "UMask": "0x80"
1015 "Counter": "0,1,2,3", string
1016 "CounterHTOff": "0,1,2,3,4,5,6,7",
1017 "EventCode": "0xA1",
1021 "UMask": "0x80"
1025 "Counter": "0,1,2,3", string
1026 "CounterHTOff": "0,1,2,3,4,5,6,7",
1027 "EventCode": "0xB1",
1029 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
1031 "UMask": "0x2"
1034 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
1035 "Counter": "0,1,2,3", string
1036 "CounterHTOff": "0,1,2,3,4,5,6,7",
1038 "EventCode": "0xB1",
1040 … "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1042 "UMask": "0x2"
1045 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
1046 "Counter": "0,1,2,3", string
1047 "CounterHTOff": "0,1,2,3,4,5,6,7",
1049 "EventCode": "0xB1",
1051 … "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1053 "UMask": "0x2"
1056 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
1057 "Counter": "0,1,2,3", string
1058 "CounterHTOff": "0,1,2,3,4,5,6,7",
1060 "EventCode": "0xB1",
1062 … "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1064 "UMask": "0x2"
1067 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
1068 "Counter": "0,1,2,3", string
1069 "CounterHTOff": "0,1,2,3,4,5,6,7",
1071 "EventCode": "0xB1",
1073 … "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1075 "UMask": "0x2"
1078 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
1079 "Counter": "0,1,2,3", string
1080 "CounterHTOff": "0,1,2,3,4,5,6,7",
1081 "EventCode": "0xB1",
1084 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1086 "UMask": "0x2"
1089 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1090 "Counter": "0,1,2,3", string
1091 "CounterHTOff": "0,1,2,3,4,5,6,7",
1093 "EventCode": "0xB1",
1095 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1097 "UMask": "0x1"
1100 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1101 "Counter": "0,1,2,3", string
1102 "CounterHTOff": "0,1,2,3,4,5,6,7",
1104 "EventCode": "0xB1",
1106 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1108 "UMask": "0x1"
1111 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1112 "Counter": "0,1,2,3", string
1113 "CounterHTOff": "0,1,2,3,4,5,6,7",
1115 "EventCode": "0xB1",
1117 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1119 "UMask": "0x1"
1122 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1123 "Counter": "0,1,2,3", string
1124 "CounterHTOff": "0,1,2,3,4,5,6,7",
1126 "EventCode": "0xB1",
1128 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1130 "UMask": "0x1"
1134 "Counter": "0,1,2,3", string
1135 "CounterHTOff": "0,1,2,3",
1137 "EventCode": "0xB1",
1141 "UMask": "0x1"
1144 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1145 "Counter": "0,1,2,3", string
1146 "CounterHTOff": "0,1,2,3,4,5,6,7",
1147 "EventCode": "0xB1",
1149 …"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask …
1151 "UMask": "0x1"
1155 "Counter": "0,1,2,3", string
1156 "CounterHTOff": "0,1,2,3,4,5,6,7",
1157 "EventCode": "0x0E",
1161 "UMask": "0x1"
1166 "Counter": "0,1,2,3", string
1167 "CounterHTOff": "0,1,2,3",
1169 "EventCode": "0x0E",
1174 "UMask": "0x1"
1177 "BriefDescription": "Number of flags-merge uops being allocated.",
1178 "Counter": "0,1,2,3", string
1179 "CounterHTOff": "0,1,2,3,4,5,6,7",
1180 "EventCode": "0x0E",
1182 "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
1184 "UMask": "0x10"
1188 "Counter": "0,1,2,3", string
1189 "CounterHTOff": "0,1,2,3,4,5,6,7",
1190 "EventCode": "0x0E",
1194 "UMask": "0x40"
1198 "Counter": "0,1,2,3", string
1199 "CounterHTOff": "0,1,2,3,4,5,6,7",
1200 "EventCode": "0x0E",
1204 "UMask": "0x20"
1208 "Counter": "0,1,2,3", string
1209 "CounterHTOff": "0,1,2,3",
1211 "EventCode": "0x0E",
1216 "UMask": "0x1"
1220 "Counter": "0,1,2,3", string
1221 "CounterHTOff": "0,1,2,3,4,5,6,7",
1222 "EventCode": "0xC2",
1226 "UMask": "0x1"
1231 "Counter": "0,1,2,3", string
1232 "CounterHTOff": "0,1,2,3",
1234 "EventCode": "0xC2",
1238 "UMask": "0x1"
1242 "Counter": "0,1,2,3", string
1243 "CounterHTOff": "0,1,2,3,4,5,6,7",
1244 "EventCode": "0xC2",
1248 "UMask": "0x2"
1252 "Counter": "0,1,2,3", string
1253 "CounterHTOff": "0,1,2,3",
1255 "EventCode": "0xC2",
1259 "UMask": "0x1"
1263 "Counter": "0,1,2,3", string
1264 "CounterHTOff": "0,1,2,3",
1266 "EventCode": "0xC2",
1270 "UMask": "0x1"