Lines Matching full:per
10 …nd undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
14 …egorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
24 …ue to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
28 …ring Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
39 …ting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
43 …: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
50 …ut was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metr…
53 … that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
57 …per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no ro…
60 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
66 "BriefDescription": "Uops Per Instruction",
72 "BriefDescription": "Instruction per taken branch",
78 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
84 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
96 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
109 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
115 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
121 "BriefDescription": "Floating Point Operations Per Cycle",
127 "BriefDescription": "Floating Point Operations Per Cycle",
139 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
151 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
157 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
163 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
169 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
175 "BriefDescription": "Instruction per taken branch",
181 "BriefDescription": "Branch instructions per taken branch. ",
187 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
191 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
213 …verage number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
231 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
237 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
243 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
249 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
280 "BriefDescription": "Giga Floating Point Operations Per Second",
304 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
322 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
328 "BriefDescription": "C3 residency percent per core",
334 "BriefDescription": "C6 residency percent per core",
340 "BriefDescription": "C7 residency percent per core",
346 "BriefDescription": "C2 residency percent per package",
352 "BriefDescription": "C3 residency percent per package",
358 "BriefDescription": "C6 residency percent per package",
364 "BriefDescription": "C7 residency percent per package",