Lines Matching +full:3 +full:- +full:6
5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
18 "Counter": "0,1,2,3,4,5,6,7",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
30 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
45 "PEBScounters": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
57 "PEBScounters": "0,1,2,3,4,5,6,7",
65 "Counter": "0,1,2,3,4,5,6,7",
69 "PEBScounters": "0,1,2,3,4,5,6,7",
77 "Counter": "0,1,2,3,4,5,6,7",
81 "PEBScounters": "0,1,2,3,4,5,6,7",
89 "Counter": "0,1,2,3,4,5,6,7",
93 "PEBScounters": "0,1,2,3,4,5,6,7",
101 "Counter": "0,1,2,3,4,5,6,7",
105 "PEBScounters": "0,1,2,3,4,5,6,7",
113 "Counter": "0,1,2,3,4,5,6,7",
117 "PEBScounters": "0,1,2,3,4,5,6,7",
125 "Counter": "0,1,2,3,4,5,6,7",
129 "PEBScounters": "0,1,2,3,4,5,6,7",
137 "Counter": "0,1,2,3,4,5,6,7",
141 "PEBScounters": "0,1,2,3,4,5,6,7",
148 "Counter": "0,1,2,3,4,5,6,7",
152 "PEBScounters": "0,1,2,3,4,5,6,7",
158 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
160 "Counter": "0,1,2,3,4,5,6,7",
164 "PEBScounters": "0,1,2,3,4,5,6,7",
172 "Counter": "0,1,2,3,4,5,6,7",
176 "PEBScounters": "0,1,2,3,4,5,6,7",
182 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
184 "Counter": "0,1,2,3,4,5,6,7",
188 "PEBScounters": "0,1,2,3,4,5,6,7",
189 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
196 "Counter": "0,1,2,3,4,5,6,7",
200 "PEBScounters": "0,1,2,3,4,5,6,7",
208 "Counter": "0,1,2,3,4,5,6,7",
212 "PEBScounters": "0,1,2,3,4,5,6,7",
220 "Counter": "0,1,2,3,4,5,6,7",
223 "PEBScounters": "0,1,2,3,4,5,6,7",
232 "Counter": "0,1,2,3,4,5,6,7",
235 "PEBScounters": "0,1,2,3,4,5,6,7",
244 "Counter": "0,1,2,3,4,5,6,7",
247 "PEBScounters": "0,1,2,3,4,5,6,7",
248 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
267 "Counter": "0,1,2,3,4,5,6,7",
270 "PEBScounters": "0,1,2,3,4,5,6,7",
290 "Counter": "0,1,2,3,4,5,6,7",
293 "PEBScounters": "0,1,2,3,4,5,6,7",
301 "Counter": "0,1,2,3",
305 "PEBScounters": "0,1,2,3",
313 "Counter": "0,1,2,3",
317 "PEBScounters": "0,1,2,3",
325 "Counter": "0,1,2,3,4,5,6,7",
329 "PEBScounters": "0,1,2,3,4,5,6,7",
337 "Counter": "0,1,2,3",
341 "PEBScounters": "0,1,2,3",
349 "Counter": "0,1,2,3",
353 "PEBScounters": "0,1,2,3",
361 "Counter": "0,1,2,3,4,5,6,7",
365 "PEBScounters": "0,1,2,3,4,5,6,7",
373 "Counter": "0,1,2,3,4,5,6,7",
377 "PEBScounters": "0,1,2,3,4,5,6,7",
385 "Counter": "0,1,2,3,4,5,6,7",
388 "PEBScounters": "0,1,2,3,4,5,6,7",
397 "Counter": "0,1,2,3,4,5,6,7",
400 "PEBScounters": "0,1,2,3,4,5,6,7",
407 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
409 "Counter": "0,1,2,3,4,5,6,7",
411 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
412 "PEBScounters": "0,1,2,3,4,5,6,7",
413 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
421 "Counter": "0,1,2,3,4,5,6,7",
424 "PEBScounters": "0,1,2,3,4,5,6,7",
433 "Counter": "0,1,2,3,4,5,6,7",
437 "PEBScounters": "0,1,2,3,4,5,6,7",
446 "Counter": "0,1,2,3",
449 "PEBScounters": "0,1,2,3",
450 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
458 "Counter": "0,1,2,3",
461 "PEBScounters": "0,1,2,3",
468 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
474 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
479 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
481 "Counter": "0,1,2,3,4,5,6,7",
485 "PEBScounters": "0,1,2,3,4,5,6,7",
486 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
492 "Counter": "0,1,2,3,4,5,6,7",
496 "PEBScounters": "0,1,2,3,4,5,6,7",
512 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
514 "Counter": "0,1,2,3,4,5,6,7",
518 "PEBScounters": "0,1,2,3,4,5,6,7",
519 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
527 "Counter": "0,1,2,3,4,5,6,7",
530 "PEBScounters": "0,1,2,3,4,5,6,7",
539 "Counter": "0,1,2,3,4,5,6,7",
542 "PEBScounters": "0,1,2,3,4,5,6,7",
551 "Counter": "0,1,2,3,4,5,6,7",
554 "PEBScounters": "0,1,2,3,4,5,6,7",
555 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
563 "Counter": "0,1,2,3",
566 "PEBScounters": "0,1,2,3",
575 "Counter": "0,1,2,3",
578 "PEBScounters": "0,1,2,3",
587 "Counter": "0,1,2,3",
590 "PEBScounters": "0,1,2,3",
599 "Counter": "0,1,2,3",
602 "PEBScounters": "0,1,2,3",
603 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
611 "Counter": "0,1,2,3",
615 "PEBScounters": "0,1,2,3",
616 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
624 "Counter": "0,1,2,3",
628 "PEBScounters": "0,1,2,3",
629 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
637 "Counter": "0,1,2,3",
640 "PEBScounters": "0,1,2,3",
641 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
649 "Counter": "0,1,2,3,4,5,6,7",
654 "PEBScounters": "0,1,2,3,4,5,6,7",
661 "BriefDescription": "Self-modifying code (SMC) detected.",
663 "Counter": "0,1,2,3,4,5,6,7",
666 "PEBScounters": "0,1,2,3,4,5,6,7",
667 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
675 "Counter": "0,1,2,3,4,5,6,7",
678 "PEBScounters": "0,1,2,3,4,5,6,7",
686 "Counter": "0,1,2,3,4,5,6,7",
696 "Counter": "0,1,2,3,4,5,6,7",
699 "PEBScounters": "0,1,2,3,4,5,6,7",
700 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
708 "Counter": "0,1,2,3,4,5,6,7",
711 "PEBScounters": "0,1,2,3,4,5,6,7",
719 "Counter": "0,1,2,3,4,5,6,7",
722 "PEBScounters": "0,1,2,3,4,5,6,7",
723 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
731 "Counter": "0,1,2,3,4,5,6,7",
737 "PEBScounters": "0,1,2,3,4,5,6,7",
738 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
744 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
746 "Counter": "0,1,2,3,4,5,6,7",
749 "PEBScounters": "0,1,2,3,4,5,6,7",
750 …-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued…
756 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
758 "Counter": "Fixed counter 3",
761 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
767 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
769 "Counter": "0,1,2,3,4,5,6,7",
772 "PEBScounters": "0,1,2,3,4,5,6,7",
773 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
781 "Counter": "0,1,2,3",
784 "PEBScounters": "0,1,2,3",
793 "Counter": "0,1,2,3,4,5,6,7",
796 "PEBScounters": "0,1,2,3,4,5,6,7",
797 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
805 "Counter": "0,1,2,3,4,5,6,7",
808 "PEBScounters": "0,1,2,3,4,5,6,7",
809 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
815 "BriefDescription": "Number of uops executed on port 2 and 3",
817 "Counter": "0,1,2,3,4,5,6,7",
820 "PEBScounters": "0,1,2,3,4,5,6,7",
821 …Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reser…
829 "Counter": "0,1,2,3,4,5,6,7",
832 "PEBScounters": "0,1,2,3,4,5,6,7",
833 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
841 "Counter": "0,1,2,3,4,5,6,7",
844 "PEBScounters": "0,1,2,3,4,5,6,7",
845 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
851 "BriefDescription": "Number of uops executed on port 6",
853 "Counter": "0,1,2,3,4,5,6,7",
856 "PEBScounters": "0,1,2,3,4,5,6,7",
857 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
865 "Counter": "0,1,2,3,4,5,6,7",
868 "PEBScounters": "0,1,2,3,4,5,6,7",
869 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
875 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
877 "Counter": "0,1,2,3,4,5,6,7",
881 "PEBScounters": "0,1,2,3,4,5,6,7",
882 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
888 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
890 "Counter": "0,1,2,3,4,5,6,7",
894 "PEBScounters": "0,1,2,3,4,5,6,7",
895 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
901 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
903 "Counter": "0,1,2,3,4,5,6,7",
904 "CounterMask": "3",
907 "PEBScounters": "0,1,2,3,4,5,6,7",
908 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
914 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
916 "Counter": "0,1,2,3,4,5,6,7",
920 "PEBScounters": "0,1,2,3,4,5,6,7",
921 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
927 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
929 "Counter": "0,1,2,3,4,5,6,7",
933 "PEBScounters": "0,1,2,3,4,5,6,7",
934 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
940 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
942 "Counter": "0,1,2,3,4,5,6,7",
946 "PEBScounters": "0,1,2,3,4,5,6,7",
947 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
953 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
955 "Counter": "0,1,2,3,4,5,6,7",
956 "CounterMask": "3",
959 "PEBScounters": "0,1,2,3,4,5,6,7",
960 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
966 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
968 "Counter": "0,1,2,3,4,5,6,7",
972 "PEBScounters": "0,1,2,3,4,5,6,7",
973 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
981 "Counter": "0,1,2,3,4,5,6,7",
986 "PEBScounters": "0,1,2,3,4,5,6,7",
993 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
995 "Counter": "0,1,2,3,4,5,6,7",
998 "PEBScounters": "0,1,2,3,4,5,6,7",
1006 "Counter": "0,1,2,3,4,5,6,7",
1009 "PEBScounters": "0,1,2,3,4,5,6,7",
1018 "Counter": "0,1,2,3,4,5,6,7",
1021 "PEBScounters": "0,1,2,3,4,5,6,7",
1030 "Counter": "0,1,2,3,4,5,6,7",
1035 "PEBScounters": "0,1,2,3,4,5,6,7",
1042 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
1044 "Counter": "0,1,2,3,4,5,6,7",
1047 "PEBScounters": "0,1,2,3,4,5,6,7",
1048 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
1056 "Counter": "0,1,2,3,4,5,6,7",
1059 "PEBScounters": "0,1,2,3,4,5,6,7",
1067 "Counter": "0,1,2,3,4,5,6,7",
1072 "PEBScounters": "0,1,2,3,4,5,6,7",
1081 "Counter": "0,1,2,3,4,5,6,7",
1086 "PEBScounters": "0,1,2,3,4,5,6,7",