Lines Matching full:per
15 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
21 "BriefDescription": "Uops Per Instruction",
27 "BriefDescription": "Instruction per taken branch",
33 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
39 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
45 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
64 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
70 "BriefDescription": "Floating Point Operations Per Cycle",
76 …"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of th…
80 …"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of t…
89 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
101 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
107 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
113 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
119 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
125 "BriefDescription": "Instruction per taken branch",
131 "BriefDescription": "Branch instructions per taken branch. ",
137 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
143 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
147 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
150 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
154 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
157 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
161 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
164 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
168 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
171 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
175 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
178 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
182 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
209 "BriefDescription": "Number of Instructions per non-speculative DSB miss",
252 …verage number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
270 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
276 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
282 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
288 …"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including spe…
294 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
300 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
306 …"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including specula…
312 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
318 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
324 … "BriefDescription": "Fill Buffer (FB) true hits per kilo instructions for retired demand loads",
337 …"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evi…
343 "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
361 "BriefDescription": "Giga Floating Point Operations Per Second",
406 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
472 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
478 "BriefDescription": "C1 residency percent per core",
484 "BriefDescription": "C6 residency percent per core",
490 "BriefDescription": "C2 residency percent per package",
496 "BriefDescription": "C6 residency percent per package",