Lines Matching +full:0 +full:xa1
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
6 "EventCode": "0x14",
9 "UMask": "0x2"
13 "Counter": "0,1,2,3",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "EventCode": "0x88",
19 "UMask": "0xff"
23 "Counter": "0,1,2,3",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "EventCode": "0x88",
28 "UMask": "0xc1"
32 "Counter": "0,1,2,3",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
34 "EventCode": "0x88",
37 "UMask": "0xc2"
41 "Counter": "0,1,2,3",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
43 "EventCode": "0x88",
46 "UMask": "0xd0"
50 "Counter": "0,1,2,3",
51 "CounterHTOff": "0,1,2,3,4,5,6,7",
52 "EventCode": "0x88",
55 "UMask": "0xc4"
59 "Counter": "0,1,2,3",
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
61 "EventCode": "0x88",
64 "UMask": "0xc8"
68 "Counter": "0,1,2,3",
69 "CounterHTOff": "0,1,2,3,4,5,6,7",
70 "EventCode": "0x88",
73 "UMask": "0x41"
77 "Counter": "0,1,2,3",
78 "CounterHTOff": "0,1,2,3,4,5,6,7",
79 "EventCode": "0x88",
82 "UMask": "0x81"
86 "Counter": "0,1,2,3",
87 "CounterHTOff": "0,1,2,3,4,5,6,7",
88 "EventCode": "0x88",
91 "UMask": "0x82"
95 "Counter": "0,1,2,3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "EventCode": "0x88",
100 "UMask": "0x90"
104 "Counter": "0,1,2,3",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
106 "EventCode": "0x88",
109 "UMask": "0x84"
113 "Counter": "0,1,2,3",
114 "CounterHTOff": "0,1,2,3,4,5,6,7",
115 "EventCode": "0x88",
118 "UMask": "0xa0"
122 "Counter": "0,1,2,3",
123 "CounterHTOff": "0,1,2,3,4,5,6,7",
124 "EventCode": "0x88",
127 "UMask": "0x88"
131 "Counter": "0,1,2,3",
132 "CounterHTOff": "0,1,2,3,4,5,6,7",
133 "EventCode": "0xC4",
140 "Counter": "0,1,2,3",
141 "CounterHTOff": "0,1,2,3",
142 "EventCode": "0xC4",
146 "UMask": "0x4"
150 "Counter": "0,1,2,3",
151 "CounterHTOff": "0,1,2,3,4,5,6,7",
152 "EventCode": "0xC4",
157 "UMask": "0x1"
161 "Counter": "0,1,2,3",
162 "CounterHTOff": "0,1,2,3,4,5,6,7",
163 "EventCode": "0xC4",
167 "UMask": "0x40"
171 "Counter": "0,1,2,3",
172 "CounterHTOff": "0,1,2,3,4,5,6,7",
173 "EventCode": "0xC4",
177 "UMask": "0x2"
181 "Counter": "0,1,2,3",
182 "CounterHTOff": "0,1,2,3,4,5,6,7",
183 "EventCode": "0xC4",
187 "UMask": "0x2"
191 "Counter": "0,1,2,3",
192 "CounterHTOff": "0,1,2,3,4,5,6,7",
193 "EventCode": "0xC4",
198 "UMask": "0x8"
202 "Counter": "0,1,2,3",
203 "CounterHTOff": "0,1,2,3,4,5,6,7",
204 "EventCode": "0xC4",
209 "UMask": "0x20"
213 "Counter": "0,1,2,3",
214 "CounterHTOff": "0,1,2,3,4,5,6,7",
215 "EventCode": "0xC4",
219 "UMask": "0x10"
223 "Counter": "0,1,2,3",
224 "CounterHTOff": "0,1,2,3,4,5,6,7",
225 "EventCode": "0x89",
229 "UMask": "0xff"
233 "Counter": "0,1,2,3",
234 "CounterHTOff": "0,1,2,3,4,5,6,7",
235 "EventCode": "0x89",
238 "UMask": "0xc1"
242 "Counter": "0,1,2,3",
243 "CounterHTOff": "0,1,2,3,4,5,6,7",
244 "EventCode": "0x89",
247 "UMask": "0xc4"
251 "Counter": "0,1,2,3",
252 "CounterHTOff": "0,1,2,3,4,5,6,7",
253 "EventCode": "0x89",
256 "UMask": "0x41"
260 "Counter": "0,1,2,3",
261 "CounterHTOff": "0,1,2,3,4,5,6,7",
262 "EventCode": "0x89",
265 "UMask": "0x81"
269 "Counter": "0,1,2,3",
270 "CounterHTOff": "0,1,2,3,4,5,6,7",
271 "EventCode": "0x89",
274 "UMask": "0x84"
278 "Counter": "0,1,2,3",
279 "CounterHTOff": "0,1,2,3,4,5,6,7",
280 "EventCode": "0x89",
283 "UMask": "0xa0"
287 "Counter": "0,1,2,3",
288 "CounterHTOff": "0,1,2,3,4,5,6,7",
289 "EventCode": "0x89",
292 "UMask": "0x88"
296 "Counter": "0,1,2,3",
297 "CounterHTOff": "0,1,2,3,4,5,6,7",
298 "EventCode": "0xC5",
305 "Counter": "0,1,2,3",
306 "CounterHTOff": "0,1,2,3",
307 "EventCode": "0xC5",
312 "UMask": "0x4"
316 "Counter": "0,1,2,3",
317 "CounterHTOff": "0,1,2,3,4,5,6,7",
318 "EventCode": "0xC5",
322 "UMask": "0x1"
326 "Counter": "0,1,2,3",
327 "CounterHTOff": "0,1,2,3,4,5,6,7",
328 "EventCode": "0xC5",
333 "UMask": "0x20"
337 "Counter": "0,1,2,3",
338 "CounterHTOff": "0,1,2,3",
339 "EventCode": "0x3c",
342 "UMask": "0x2"
346 "Counter": "0,1,2,3",
347 "CounterHTOff": "0,1,2,3,4,5,6,7",
348 "EventCode": "0x3C",
352 "UMask": "0x1"
357 "Counter": "0,1,2,3",
358 "CounterHTOff": "0,1,2,3,4,5,6,7",
359 "EventCode": "0x3C",
363 "UMask": "0x1"
367 "Counter": "0,1,2,3",
368 "CounterHTOff": "0,1,2,3,4,5,6,7",
369 "EventCode": "0x3C",
372 "UMask": "0x2"
381 "UMask": "0x3"
385 "Counter": "0,1,2,3",
386 "CounterHTOff": "0,1,2,3,4,5,6,7",
387 "EventCode": "0x3C",
391 "UMask": "0x1"
396 "Counter": "0,1,2,3",
397 "CounterHTOff": "0,1,2,3,4,5,6,7",
398 "EventCode": "0x3C",
402 "UMask": "0x1"
411 "UMask": "0x2"
420 "UMask": "0x2"
424 "Counter": "0,1,2,3",
425 "CounterHTOff": "0,1,2,3,4,5,6,7",
426 "EventCode": "0x3C",
434 "Counter": "0,1,2,3",
435 "CounterHTOff": "0,1,2,3,4,5,6,7",
436 "EventCode": "0x3C",
445 "EventCode": "0xA3",
449 "UMask": "0x8"
453 "Counter": "0,1,2,3",
454 "CounterHTOff": "0,1,2,3,4,5,6,7",
457 "EventCode": "0xa3",
461 "UMask": "0x1"
465 "Counter": "0,1,2,3",
466 "CounterHTOff": "0,1,2,3",
468 "EventCode": "0xA3",
472 "UMask": "0x2"
476 "Counter": "0,1,2,3",
477 "CounterHTOff": "0,1,2,3",
479 "EventCode": "0xA3",
483 "UMask": "0x4"
490 "EventCode": "0xA3",
492 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.",
494 "UMask": "0xc"
498 "Counter": "0,1,2,3",
499 "CounterHTOff": "0,1,2,3",
502 "EventCode": "0xa3",
506 "UMask": "0x5"
510 "Counter": "0,1,2,3",
511 "CounterHTOff": "0,1,2,3",
513 "EventCode": "0xA3",
517 "UMask": "0x6"
521 "Counter": "0,1,2,3",
522 "CounterHTOff": "0,1,2,3,4,5,6,7",
523 "EventCode": "0x87",
527 "UMask": "0x4"
531 "Counter": "0,1,2,3",
532 "CounterHTOff": "0,1,2,3,4,5,6,7",
533 "EventCode": "0x87",
537 "UMask": "0x1"
541 "Counter": "Fixed counter 0",
542 "CounterHTOff": "Fixed counter 0",
547 "UMask": "0x1"
551 "Counter": "0,1,2,3",
552 "CounterHTOff": "0,1,2,3,4,5,6,7",
554 "EventCode": "0xC0",
564 "EventCode": "0xC0",
569 "UMask": "0x1"
573 "Counter": "0,1,2,3",
574 "CounterHTOff": "0,1,2,3,4,5,6,7",
575 "EventCode": "0xC0",
579 "UMask": "0x2"
583 "Counter": "0,1,2,3",
584 "CounterHTOff": "0,1,2,3,4,5,6,7",
586 "EventCode": "0x0D",
590 "UMask": "0x3"
595 "Counter": "0,1,2,3",
596 "CounterHTOff": "0,1,2,3,4,5,6,7",
598 "EventCode": "0x0D",
602 "UMask": "0x3"
606 "Counter": "0,1,2,3",
607 "CounterHTOff": "0,1,2,3,4,5,6,7",
608 "EventCode": "0x03",
612 "UMask": "0x8"
616 "Counter": "0,1,2,3",
617 "CounterHTOff": "0,1,2,3,4,5,6,7",
618 "EventCode": "0x03",
622 "UMask": "0x2"
626 "Counter": "0,1,2,3",
627 "CounterHTOff": "0,1,2,3,4,5,6,7",
628 "EventCode": "0x07",
632 "UMask": "0x1"
636 "Counter": "0,1,2,3",
637 "CounterHTOff": "0,1,2,3,4,5,6,7",
638 "EventCode": "0x4c",
642 "UMask": "0x2"
646 "Counter": "0,1,2,3",
647 "CounterHTOff": "0,1,2,3,4,5,6,7",
648 "EventCode": "0x4c",
652 "UMask": "0x1"
656 "Counter": "0,1,2,3",
657 "CounterHTOff": "0,1,2,3,4,5,6,7",
659 "EventCode": "0xA8",
662 "UMask": "0x1"
666 "Counter": "0,1,2,3",
667 "CounterHTOff": "0,1,2,3,4,5,6,7",
669 "EventCode": "0xA8",
672 "UMask": "0x1"
676 "Counter": "0,1,2,3",
677 "CounterHTOff": "0,1,2,3,4,5,6,7",
678 "EventCode": "0xa8",
682 "UMask": "0x1"
686 "Counter": "0,1,2,3",
687 "CounterHTOff": "0,1,2,3,4,5,6,7",
690 "EventCode": "0xC3",
693 "UMask": "0x1"
697 "Counter": "0,1,2,3",
698 "CounterHTOff": "0,1,2,3,4,5,6,7",
699 "EventCode": "0xC3",
702 "UMask": "0x1"
705 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
706 "Counter": "0,1,2,3",
707 "CounterHTOff": "0,1,2,3,4,5,6,7",
708 "EventCode": "0xC3",
711 "UMask": "0x20"
715 "Counter": "0,1,2,3",
716 "CounterHTOff": "0,1,2,3,4,5,6,7",
717 "EventCode": "0xC3",
721 "UMask": "0x4"
725 "Counter": "0,1,2,3",
726 "CounterHTOff": "0,1,2,3,4,5,6,7",
727 "EventCode": "0x58",
731 "UMask": "0x1"
735 "Counter": "0,1,2,3",
736 "CounterHTOff": "0,1,2,3,4,5,6,7",
737 "EventCode": "0x58",
741 "UMask": "0x4"
745 "Counter": "0,1,2,3",
746 "CounterHTOff": "0,1,2,3,4,5,6,7",
747 "EventCode": "0xC1",
751 "UMask": "0x40"
755 "Counter": "0,1,2,3",
756 "CounterHTOff": "0,1,2,3,4,5,6,7",
758 "EventCode": "0xA2",
762 "UMask": "0x1"
766 "Counter": "0,1,2,3",
767 "CounterHTOff": "0,1,2,3,4,5,6,7",
768 "EventCode": "0xA2",
771 "UMask": "0x10"
775 "Counter": "0,1,2,3",
776 "CounterHTOff": "0,1,2,3,4,5,6,7",
777 "EventCode": "0xA2",
780 "UMask": "0x4"
784 "Counter": "0,1,2,3",
785 "CounterHTOff": "0,1,2,3,4,5,6,7",
786 "EventCode": "0xA2",
790 "UMask": "0x8"
794 "Counter": "0,1,2,3",
795 "CounterHTOff": "0,1,2,3,4,5,6,7",
796 "EventCode": "0xCC",
800 "UMask": "0x20"
804 "Counter": "0,1,2,3",
805 "CounterHTOff": "0,1,2,3,4,5,6,7",
806 "EventCode": "0x5E",
810 "UMask": "0x1"
814 "Counter": "0,1,2,3",
815 "CounterHTOff": "0,1,2,3,4,5,6,7",
818 "EventCode": "0x5E",
822 "UMask": "0x1"
825 "BriefDescription": "Cycles per thread when uops are executed in port 0.",
826 "Counter": "0,1,2,3",
827 "CounterHTOff": "0,1,2,3,4,5,6,7",
828 "EventCode": "0xA1",
831 "UMask": "0x1"
835 "Counter": "0,1,2,3",
836 "CounterHTOff": "0,1,2,3,4,5,6,7",
837 "EventCode": "0xA1",
840 "UMask": "0x2"
844 "Counter": "0,1,2,3",
845 "CounterHTOff": "0,1,2,3,4,5,6,7",
846 "EventCode": "0xA1",
849 "UMask": "0x4"
853 "Counter": "0,1,2,3",
854 "CounterHTOff": "0,1,2,3,4,5,6,7",
855 "EventCode": "0xA1",
858 "UMask": "0x8"
862 "Counter": "0,1,2,3",
863 "CounterHTOff": "0,1,2,3,4,5,6,7",
864 "EventCode": "0xA1",
867 "UMask": "0x10"
871 "Counter": "0,1,2,3",
872 "CounterHTOff": "0,1,2,3,4,5,6,7",
873 "EventCode": "0xA1",
876 "UMask": "0x20"
880 "Counter": "0,1,2,3",
881 "CounterHTOff": "0,1,2,3,4,5,6,7",
882 "EventCode": "0xA1",
885 "UMask": "0x40"
889 "Counter": "0,1,2,3",
890 "CounterHTOff": "0,1,2,3,4,5,6,7",
891 "EventCode": "0xA1",
894 "UMask": "0x80"
898 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3,4,5,6,7",
901 "EventCode": "0xB1",
905 "UMask": "0x2"
909 "Counter": "0,1,2,3",
910 "CounterHTOff": "0,1,2,3,4,5,6,7",
913 "EventCode": "0xb1",
916 "UMask": "0x2"
920 "Counter": "0,1,2,3",
921 "CounterHTOff": "0,1,2,3,4,5,6,7",
924 "EventCode": "0xb1",
927 "UMask": "0x2"
931 "Counter": "0,1,2,3",
932 "CounterHTOff": "0,1,2,3,4,5,6,7",
935 "EventCode": "0xb1",
938 "UMask": "0x2"
942 "Counter": "0,1,2,3",
943 "CounterHTOff": "0,1,2,3,4,5,6,7",
946 "EventCode": "0xb1",
949 "UMask": "0x2"
953 "Counter": "0,1,2,3",
954 "CounterHTOff": "0,1,2,3,4,5,6,7",
956 "EventCode": "0xb1",
960 "UMask": "0x2"
964 "Counter": "0,1,2,3",
965 "CounterHTOff": "0,1,2,3",
968 "EventCode": "0xB1",
972 "UMask": "0x1"
976 "Counter": "0,1,2,3",
977 "CounterHTOff": "0,1,2,3",
980 "EventCode": "0xB1",
984 "UMask": "0x1"
988 "Counter": "0,1,2,3",
989 "CounterHTOff": "0,1,2,3",
992 "EventCode": "0xB1",
996 "UMask": "0x1"
1000 "Counter": "0,1,2,3",
1001 "CounterHTOff": "0,1,2,3",
1004 "EventCode": "0xB1",
1007 "UMask": "0x1"
1011 "Counter": "0,1,2,3",
1012 "CounterHTOff": "0,1,2,3",
1015 "EventCode": "0xB1",
1019 "UMask": "0x1"
1022 "BriefDescription": "Cycles per thread when uops are executed in port 0",
1023 "Counter": "0,1,2,3",
1024 "CounterHTOff": "0,1,2,3,4,5,6,7",
1025 "EventCode": "0xA1",
1027 "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
1029 "UMask": "0x1"
1033 "BriefDescription": "Cycles per core when uops are executed in port 0.",
1034 "Counter": "0,1,2,3",
1035 "CounterHTOff": "0,1,2,3,4,5,6,7",
1036 "EventCode": "0xA1",
1038 "PublicDescription": "Cycles per core when uops are exectuted in port 0.",
1040 "UMask": "0x1"
1044 "Counter": "0,1,2,3",
1045 "CounterHTOff": "0,1,2,3,4,5,6,7",
1046 "EventCode": "0xA1",
1050 "UMask": "0x2"
1055 "Counter": "0,1,2,3",
1056 "CounterHTOff": "0,1,2,3,4,5,6,7",
1057 "EventCode": "0xA1",
1061 "UMask": "0x2"
1065 "Counter": "0,1,2,3",
1066 "CounterHTOff": "0,1,2,3,4,5,6,7",
1067 "EventCode": "0xA1",
1071 "UMask": "0x4"
1076 "Counter": "0,1,2,3",
1077 "CounterHTOff": "0,1,2,3,4,5,6,7",
1078 "EventCode": "0xA1",
1081 "UMask": "0x4"
1085 "Counter": "0,1,2,3",
1086 "CounterHTOff": "0,1,2,3,4,5,6,7",
1087 "EventCode": "0xA1",
1091 "UMask": "0x8"
1096 "Counter": "0,1,2,3",
1097 "CounterHTOff": "0,1,2,3,4,5,6,7",
1098 "EventCode": "0xA1",
1101 "UMask": "0x8"
1105 "Counter": "0,1,2,3",
1106 "CounterHTOff": "0,1,2,3,4,5,6,7",
1107 "EventCode": "0xA1",
1111 "UMask": "0x10"
1116 "Counter": "0,1,2,3",
1117 "CounterHTOff": "0,1,2,3,4,5,6,7",
1118 "EventCode": "0xA1",
1122 "UMask": "0x10"
1126 "Counter": "0,1,2,3",
1127 "CounterHTOff": "0,1,2,3,4,5,6,7",
1128 "EventCode": "0xA1",
1132 "UMask": "0x20"
1137 "Counter": "0,1,2,3",
1138 "CounterHTOff": "0,1,2,3,4,5,6,7",
1139 "EventCode": "0xA1",
1143 "UMask": "0x20"
1147 "Counter": "0,1,2,3",
1148 "CounterHTOff": "0,1,2,3,4,5,6,7",
1149 "EventCode": "0xA1",
1153 "UMask": "0x40"
1158 "Counter": "0,1,2,3",
1159 "CounterHTOff": "0,1,2,3,4,5,6,7",
1160 "EventCode": "0xA1",
1164 "UMask": "0x40"
1168 "Counter": "0,1,2,3",
1169 "CounterHTOff": "0,1,2,3,4,5,6,7",
1170 "EventCode": "0xA1",
1174 "UMask": "0x80"
1179 "Counter": "0,1,2,3",
1180 "CounterHTOff": "0,1,2,3,4,5,6,7",
1181 "EventCode": "0xA1",
1184 "UMask": "0x80"
1188 "Counter": "0,1,2,3",
1189 "CounterHTOff": "0,1,2,3,4,5,6,7",
1190 "EventCode": "0x0E",
1194 "UMask": "0x1"
1199 "Counter": "0,1,2,3",
1200 "CounterHTOff": "0,1,2,3",
1202 "EventCode": "0x0E",
1206 "UMask": "0x1"
1210 "Counter": "0,1,2,3",
1211 "CounterHTOff": "0,1,2,3,4,5,6,7",
1212 "EventCode": "0x0E",
1216 "UMask": "0x10"
1220 "Counter": "0,1,2,3",
1221 "CounterHTOff": "0,1,2,3,4,5,6,7",
1222 "EventCode": "0x0E",
1226 "UMask": "0x40"
1230 "Counter": "0,1,2,3",
1231 "CounterHTOff": "0,1,2,3,4,5,6,7",
1232 "EventCode": "0x0E",
1236 "UMask": "0x20"
1240 "Counter": "0,1,2,3",
1241 "CounterHTOff": "0,1,2,3",
1243 "EventCode": "0x0E",
1247 "UMask": "0x1"
1251 "Counter": "0,1,2,3",
1252 "CounterHTOff": "0,1,2,3,4,5,6,7",
1253 "EventCode": "0xC2",
1258 "UMask": "0x1"
1263 "Counter": "0,1,2,3",
1264 "CounterHTOff": "0,1,2,3",
1266 "EventCode": "0xC2",
1270 "UMask": "0x1"
1274 "Counter": "0,1,2,3",
1275 "CounterHTOff": "0,1,2,3,4,5,6,7",
1276 "EventCode": "0xC2",
1281 "UMask": "0x2"
1285 "Counter": "0,1,2,3",
1286 "CounterHTOff": "0,1,2,3",
1288 "EventCode": "0xC2",
1292 "UMask": "0x1"
1296 "Counter": "0,1,2,3",
1297 "CounterHTOff": "0,1,2,3",
1299 "EventCode": "0xC2",
1303 "UMask": "0x1"