Lines Matching +full:average +full:- +full:on

7 …on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch…
14 …on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch…
18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4…
21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY …
28 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
33 …"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUE…
36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
40 …- ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED…
43 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
50 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
57 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
84 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
96 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
102         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
108         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
114 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
120 …   "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
126 …"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
180 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in co…
184 …ctual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency ma…
187 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
193         "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
199         "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
205         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
242         "BriefDescription": "Average CPU Utilization",
248         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
254         "BriefDescription": "Average Frequency Utilization relative nominal frequency",
261 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #…
278         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
284 …"BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Acc…
290 …"BriefDescription": "Average number of parallel data read requests to external memory. Accounts fo…
296         "BriefDescription": "Socket actual clocks when any core is active on that socket",
309         "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
315         "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
321         "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
327         "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
333         "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
339         "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
345         "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",