Lines Matching +full:7 +full:k

5         "CounterHTOff": "0,1,2,3,4,5,6,7",
15         "CounterHTOff": "0,1,2,3,4,5,6,7",
25         "CounterHTOff": "0,1,2,3,4,5,6,7",
35         "CounterHTOff": "0,1,2,3,4,5,6,7",
43         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
45         "CounterHTOff": "0,1,2,3,4,5,6,7",
48 …"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB le…
55         "CounterHTOff": "0,1,2,3,4,5,6,7",
65         "CounterHTOff": "0,1,2,3,4,5,6,7",
74         "CounterHTOff": "0,1,2,3,4,5,6,7",
82 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
84         "CounterHTOff": "0,1,2,3,4,5,6,7",
87 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
94         "CounterHTOff": "0,1,2,3,4,5,6,7",
104         "CounterHTOff": "0,1,2,3,4,5,6,7",
107 …  "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
114         "CounterHTOff": "0,1,2,3,4,5,6,7",
124         "CounterHTOff": "0,1,2,3,4,5,6,7",
134         "CounterHTOff": "0,1,2,3,4,5,6,7",
142         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
144         "CounterHTOff": "0,1,2,3,4,5,6,7",
147 …"PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB l…
154         "CounterHTOff": "0,1,2,3,4,5,6,7",
157 …ption": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
164         "CounterHTOff": "0,1,2,3,4,5,6,7",
173         "CounterHTOff": "0,1,2,3,4,5,6,7",
181         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
183         "CounterHTOff": "0,1,2,3,4,5,6,7",
186 …ption": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
193         "CounterHTOff": "0,1,2,3,4,5,6,7",
203         "CounterHTOff": "0,1,2,3,4,5,6,7",
210 …      "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
212         "CounterHTOff": "0,1,2,3,4,5,6,7",
215         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
222         "CounterHTOff": "0,1,2,3,4,5,6,7",
232         "CounterHTOff": "0,1,2,3,4,5,6,7",
242         "CounterHTOff": "0,1,2,3,4,5,6,7",
250         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
252         "CounterHTOff": "0,1,2,3,4,5,6,7",
255         "PublicDescription": "ITLB misses that hit STLB (4K).",
262         "CounterHTOff": "0,1,2,3,4,5,6,7",
272         "CounterHTOff": "0,1,2,3,4,5,6,7",
281         "CounterHTOff": "0,1,2,3,4,5,6,7",
289         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
291         "CounterHTOff": "0,1,2,3,4,5,6,7",
294         "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
301         "CounterHTOff": "0,1,2,3,4,5,6,7",
467         "CounterHTOff": "0,1,2,3,4,5,6,7",
477         "CounterHTOff": "0,1,2,3,4,5,6,7",