Lines Matching +full:per +full:- +full:cpu

7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
10 …nd undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4…
21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
24 …ue to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY …
28 …-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work…
33 …"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUE…
36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
39 …ting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
40 …- ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED…
43 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
50 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
53 … that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
57 …-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no r…
60         "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
66         "BriefDescription": "Uops Per Instruction",
72         "BriefDescription": "Instruction per taken branch",
78         "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
84 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
96 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
102         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
108         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
114 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
115 …cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) ) i…
120 …   "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
132         "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
138         "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
144         "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
150 …    "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
156         "BriefDescription": "Instruction per taken branch",
162         "BriefDescription": "Branch instructions per taken branch. ",
180 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in co…
184 … Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overesti…
187 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
205         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
211         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
217         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
223         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
242         "BriefDescription": "Average CPU Utilization",
261 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #…
272         "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
296 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
302         "BriefDescription": "C3 residency percent per core",
303         "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
308         "BriefDescription": "C6 residency percent per core",
309         "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
314         "BriefDescription": "C7 residency percent per core",
315         "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
320         "BriefDescription": "C2 residency percent per package",
321         "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
326         "BriefDescription": "C3 residency percent per package",
327         "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
332         "BriefDescription": "C6 residency percent per package",
333         "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
338         "BriefDescription": "C7 residency percent per package",
339         "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",