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10 …nd undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
14 …egorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
24 …ue to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
28 …ring Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
39 …ting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
43 …: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
50 …ut was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metr…
53 … that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
57 …per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no ro…
60 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
66 "BriefDescription": "Uops Per Instruction",
72 "BriefDescription": "Instruction per taken branch",
78 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
84 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
96 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
102 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
108 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
120 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
132 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
138 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
144 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
150 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
156 "BriefDescription": "Instruction per taken branch",
162 "BriefDescription": "Branch instructions per taken branch. ",
187 …verage number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
205 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
211 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
217 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
223 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
272 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
296 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
302 "BriefDescription": "C3 residency percent per core",
308 "BriefDescription": "C6 residency percent per core",
314 "BriefDescription": "C7 residency percent per core",
320 "BriefDescription": "C2 residency percent per package",
326 "BriefDescription": "C3 residency percent per package",
332 "BriefDescription": "C6 residency percent per package",
338 "BriefDescription": "C7 residency percent per package",