Lines Matching +full:0 +full:x10001
5 "Counter": "0,1,2,3",
7 "EventCode": "0x63",
10 "PEBScounters": "0,1,2,3",
16 "Counter": "0,1,2,3",
17 "EventCode": "0x63",
19 "PEBScounters": "0,1,2,3",
22 "UMask": "0x2"
27 "Counter": "0,1,2,3",
28 "EventCode": "0x63",
31 "PEBScounters": "0,1,2,3",
33 "UMask": "0x2"
38 "Counter": "0,1,2,3",
39 "EventCode": "0x63",
42 "PEBScounters": "0,1,2,3",
44 "UMask": "0x1"
49 "Counter": "0,1,2,3",
50 "EventCode": "0x63",
52 "PEBScounters": "0,1,2,3",
55 "UMask": "0x1"
60 "Counter": "0,1,2,3",
62 "EventCode": "0x63",
64 "PEBScounters": "0,1,2,3",
71 "Counter": "0,1,2,3",
72 "EventCode": "0x34",
75 "PEBScounters": "0,1,2,3",
77 "UMask": "0x4"
82 "Counter": "0,1,2,3",
83 "EventCode": "0x34",
86 "PEBScounters": "0,1,2,3",
88 "UMask": "0x1"
93 "Counter": "0,1,2,3",
94 "EventCode": "0x34",
97 "PEBScounters": "0,1,2,3",
99 "UMask": "0x2"
104 "Counter": "0,1,2,3",
105 "EventCode": "0xcb",
108 "PEBScounters": "0,1,2,3",
109 …ts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of wheth…
111 "UMask": "0x2"
116 "Counter": "0,1,2,3",
117 "EventCode": "0xcb",
120 "PEBScounters": "0,1,2,3",
121 …AGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). Thi…
123 "UMask": "0x4"
128 "Counter": "0,1,2,3",
129 "EventCode": "0xcb",
132 "PEBScounters": "0,1,2,3",
134 "UMask": "0x1"
138 "Counter": "0,1,2,3",
139 "EventCode": "0XB7",
141 "MSRIndex": "0x1a6,0x1a7",
142 "MSRValue": "0x10001",
146 "UMask": "0x1"
150 "Counter": "0,1,2,3",
151 "EventCode": "0XB7",
153 "MSRIndex": "0x1a6,0x1a7",
154 "MSRValue": "0x10001",
158 "UMask": "0x1"
162 "Counter": "0,1,2,3",
163 "EventCode": "0XB7",
165 "MSRIndex": "0x1a6,0x1a7",
166 "MSRValue": "0x10002",
170 "UMask": "0x1"