Lines Matching +full:3 +full:- +full:point

3 …riefDescription": "Counts once for most SIMD 128-bit packed computational double precision floatin…
4         "Counter": "0,1,2,3",
5         "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …-bit packed computational double precision floating-point instructions retired; some instructions …
13 …riefDescription": "Counts once for most SIMD 128-bit packed computational single precision floatin…
14         "Counter": "0,1,2,3",
15         "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …-bit packed computational single precision floating-point instructions retired; some instructions …
23 …riefDescription": "Counts once for most SIMD 256-bit packed double computational precision floatin…
24         "Counter": "0,1,2,3",
25         "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-bit packed double computational precision floating-point instructions retired; some instructions …
33 …riefDescription": "Counts once for most SIMD 256-bit packed single computational precision floatin…
34         "Counter": "0,1,2,3",
35         "CounterHTOff": "0,1,2,3,4,5,6,7",
38 …-bit packed single computational precision floating-point instructions retired; some instructions …
43 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
44         "Counter": "0,1,2,3",
45         "CounterHTOff": "0,1,2,3,4,5,6,7",
48 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
53 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
54         "Counter": "0,1,2,3",
55         "CounterHTOff": "0,1,2,3,4,5,6,7",
58 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
63 …"Counts once for most SIMD scalar computational double precision floating-point instructions retir…
64         "Counter": "0,1,2,3",
65         "CounterHTOff": "0,1,2,3,4,5,6,7",
68 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
73 …"Counts once for most SIMD scalar computational single precision floating-point instructions retir…
74         "Counter": "0,1,2,3",
75         "CounterHTOff": "0,1,2,3,4,5,6,7",
78 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
83 …   "BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.",
84         "Counter": "0,1,2,3",
85         "CounterHTOff": "0,1,2,3,4,5,6,7",
88 …licDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floatin…
93 …   "BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.",
94         "Counter": "0,1,2,3",
95         "CounterHTOff": "0,1,2,3,4,5,6,7",
98 …licDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floatin…
103 …   "BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.",
104         "Counter": "0,1,2,3",
105         "CounterHTOff": "0,1,2,3,4,5,6,7",
108 …licDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floatin…
114         "Counter": "0,1,2,3",
115         "CounterHTOff": "0,1,2,3,4,5,6,7",