Lines Matching +full:7 +full:k

5         "CounterHTOff": "0,1,2,3,4,5,6,7",
9 …event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
16         "CounterHTOff": "0,1,2,3,4,5,6,7",
25         "CounterHTOff": "0,1,2,3,4,5,6,7",
32         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K).",
34         "CounterHTOff": "0,1,2,3,4,5,6,7",
43         "CounterHTOff": "0,1,2,3,4,5,6,7",
53         "CounterHTOff": "0,1,2,3,4,5,6,7",
64         "CounterHTOff": "0,1,2,3,4,5,6,7",
73 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
75         "CounterHTOff": "0,1,2,3,4,5,6,7",
79 …nt counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page…
86         "CounterHTOff": "0,1,2,3,4,5,6,7",
97         "CounterHTOff": "0,1,2,3,4,5,6,7",
101 …vent counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
108         "CounterHTOff": "0,1,2,3,4,5,6,7",
117         "CounterHTOff": "0,1,2,3,4,5,6,7",
124         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K).",
126         "CounterHTOff": "0,1,2,3,4,5,6,7",
135         "CounterHTOff": "0,1,2,3,4,5,6,7",
145         "CounterHTOff": "0,1,2,3,4,5,6,7",
156         "CounterHTOff": "0,1,2,3,4,5,6,7",
165         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
167         "CounterHTOff": "0,1,2,3,4,5,6,7",
171 …t counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page…
178         "CounterHTOff": "0,1,2,3,4,5,6,7",
189         "CounterHTOff": "0,1,2,3,4,5,6,7",
197 …      "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
199         "CounterHTOff": "0,1,2,3,4,5,6,7",
209         "CounterHTOff": "0,1,2,3,4,5,6,7",
213 …vent counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
220         "CounterHTOff": "0,1,2,3,4,5,6,7",
229         "CounterHTOff": "0,1,2,3,4,5,6,7",
236         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K).",
238         "CounterHTOff": "0,1,2,3,4,5,6,7",
247         "CounterHTOff": "0,1,2,3,4,5,6,7",
257         "CounterHTOff": "0,1,2,3,4,5,6,7",
268         "CounterHTOff": "0,1,2,3,4,5,6,7",
277         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
279         "CounterHTOff": "0,1,2,3,4,5,6,7",
283 …t counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page…
290         "CounterHTOff": "0,1,2,3,4,5,6,7",
371         "CounterHTOff": "0,1,2,3,4,5,6,7",
381         "CounterHTOff": "0,1,2,3,4,5,6,7",