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10 …nd undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
14 …egorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
24 …ue to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
28 …ring Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
39 …ting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
43 …: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
50 …ut was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metr…
53 … that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
57 …per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no ro…
60 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
66 "BriefDescription": "Uops Per Instruction",
72 "BriefDescription": "Instruction per taken branch",
78 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
84 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
96 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
109 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
115 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
121 "BriefDescription": "Floating Point Operations Per Cycle",
127 "BriefDescription": "Floating Point Operations Per Cycle",
133 …"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of th…
137 …"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of t…
140 …ctual per-core usage of the Floating Point execution units (regardless of the vector width). SMT v…
144 …per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 …
153 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
159 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
165 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
177 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
183 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
189 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
195 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
201 "BriefDescription": "Instruction per taken branch",
207 "BriefDescription": "Branch instructions per taken branch.",
213 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
219 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
223 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
226 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
230 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
233 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
237 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
240 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
244 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
247 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
251 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
273 …verage number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
291 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
297 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
303 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
309 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
315 …"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including specula…
321 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
327 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
333 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
364 "BriefDescription": "Giga Floating Point Operations Per Second",
388 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
418 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
424 "BriefDescription": "C3 residency percent per core",
430 "BriefDescription": "C6 residency percent per core",
436 "BriefDescription": "C7 residency percent per core",
442 "BriefDescription": "C2 residency percent per package",
448 "BriefDescription": "C3 residency percent per package",
454 "BriefDescription": "C6 residency percent per package",
460 "BriefDescription": "C7 residency percent per package",