Lines Matching +full:2 +full:- +full:point

3 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
4         "Counter": "0,1,2,3",
5         "CounterHTOff": "0,1,2,3",
12 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
13         "Counter": "0,1,2,3",
14         "CounterHTOff": "0,1,2,3",
21 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
22         "Counter": "0,1,2,3",
23         "CounterHTOff": "0,1,2,3",
30 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
31         "Counter": "0,1,2,3",
32         "CounterHTOff": "0,1,2,3",
39 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
40         "Counter": "0,1,2,3",
41         "CounterHTOff": "0,1,2,3",
48 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
49         "Counter": "0,1,2,3",
50         "CounterHTOff": "0,1,2,3",
57 …-point instructions retired; some instructions will count twice as noted below. Each count represe…
58         "Counter": "0,1,2,3",
59         "CounterHTOff": "0,1,2,3",
66 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
67         "Counter": "0,1,2,3",
68         "CounterHTOff": "0,1,2,3",
75 …-point instructions retired; some instructions will count twice as noted below.  Each count repres…
76         "Counter": "0,1,2,3",
77         "CounterHTOff": "0,1,2,3",
84 …-point instructions retired; some instructions will count twice as noted below. Applies to SSE* an…
85         "Counter": "0,1,2,3",
86         "CounterHTOff": "0,1,2,3",
94         "Counter": "0,1,2,3",
95         "CounterHTOff": "0,1,2,3",
105         "Counter": "0,1,2,3",
106         "CounterHTOff": "0,1,2,3,4,5,6,7",
109 …ssist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes onl…
115         "Counter": "0,1,2,3",
116         "CounterHTOff": "0,1,2,3,4,5,6,7",
119 …point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination regis…
125         "Counter": "0,1,2,3",
126         "CounterHTOff": "0,1,2,3,4,5,6,7",
129 …"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operati…
135         "Counter": "0,1,2,3",
136         "CounterHTOff": "0,1,2,3,4,5,6,7",
139 …"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (n…
145         "Counter": "0,1,2,3",
146         "CounterHTOff": "0,1,2,3,4,5,6,7",
154         "Counter": "0,1,2,3",
155         "CounterHTOff": "0,1,2,3,4,5,6,7",
162 …   "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
163         "Counter": "0,1,2,3",
164         "CounterHTOff": "0,1,2,3,4,5,6,7",
168 …"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when …
173         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
174         "Counter": "0,1,2,3",
175         "CounterHTOff": "0,1,2,3,4,5,6,7",
179 …"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when …
184 …"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file…
185         "Counter": "0,1,2,3",
186         "CounterHTOff": "0,1,2,3",
189 …"PublicDescription": "This event counts the number of micro-operations cancelled after they were d…