Lines Matching +full:per +full:- +full:rate

7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
10 …nd undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4…
21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
24 …ue to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY …
28 …-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work…
33 …"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUE…
36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
39 …ting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
40 …- ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED…
43 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
50 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
53 … that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
57 …-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no r…
60         "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
66         "BriefDescription": "Uops Per Instruction",
72         "BriefDescription": "Instruction per taken branch",
78         "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
84 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
96 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
102         "BriefDescription": "The ratio of Executed- by Issued-Uops",
106 …ion": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. R…
109         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
115         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
121         "BriefDescription": "Floating Point Operations Per Cycle",
127         "BriefDescription": "Floating Point Operations Per Cycle",
133 …"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of th…
137 …ion": "Actual per-core usage of the Floating Point execution units (regardless of the vector width…
140 …ctual per-core usage of the Floating Point execution units (regardless of the vector width). SMT v…
144 …per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 …
147 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
153 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
154 …BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_…
159 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
160 …BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_…
165 …   "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
177         "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
183         "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
189         "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
195 …    "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
201         "BriefDescription": "Instruction per taken branch",
207         "BriefDescription": "Branch instructions per taken branch. ",
213 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
219 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
223 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
226 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
230 …Description": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number me…
233 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
237 …Description": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number me…
240 …riefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
244 …blicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means …
247 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
251 …PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
266 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in co…
270 … Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overesti…
273 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
291         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
297         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
303         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
309 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
315 …"BriefDescription": "L2 cache misses per kilo instruction for all demand loads  (including specula…
321 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
322         "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY",
327 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculati…
333         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
364         "BriefDescription": "Giga Floating Point Operations Per Second",
377 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #…
388         "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
412 …per Far Branch ( Far Branches apply upon transition from application to operating system, handling…
418         "BriefDescription": "C3 residency percent per core",
419         "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
424         "BriefDescription": "C6 residency percent per core",
425         "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
430         "BriefDescription": "C7 residency percent per core",
431         "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
436         "BriefDescription": "C2 residency percent per package",
437         "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
442         "BriefDescription": "C3 residency percent per package",
443         "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
448         "BriefDescription": "C6 residency percent per package",
449         "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
454         "BriefDescription": "C7 residency percent per package",
455         "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",